Chip Industry Week In Review

By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Chip Industry Technical Paper Roundup: Mar. 11

By Liz Allan - 11 Mar, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=205 /] More ReadingTechnical Paper Library home » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections

By Technical Paper Link - 07 Mar, 2024 - Comments: 0

A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

Chip Industry Technical Paper Roundup: Jan. 23

By Liz Allan - 23 Jan, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=189 /] More ReadingTechnical Paper Library home » read more

Training Large LLM Models With Billions To Trillion Parameters On ORNL’s Frontier Supercomputer

By Technical Paper Link - 16 Jan, 2024 - Comments: 0

A technical paper titled “Optimizing Distributed Training on Frontier for Large Language Models” was published by researchers at Oak Ridge National Laboratory (ORNL) and Universite Paris-Saclay. Abstract: "Large language models (LLMs) have demonstrated remarkable success as foundational models, benefiting various downstream applications through fine-tuning. Recent studies on loss scaling ... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy

By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

Chip Industry’s Technical Paper Roundup: Feb. 28

By Linda Christensen - 28 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=83 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Formal Processor Model Providing Secure Speculation For The Constant-Time Policy

By Technical Paper Link - 24 Feb, 2023 - Comments: 0

A technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy (Extended version)" was published by researchers at imec-DistriNet at KU Leuven, CEA, List, Université Paris Saclay and INRIA. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-time programs under a no... » read more

Field-free spin-orbit torque-induced switching of perpendicular magnetization in a ferrimagnetic layer with a vertical composition gradient

By Technical Paper Link - 04 Jan, 2022 - Comments: 0

Abstract "Current-induced spin-orbit torques (SOTs) are of interest for fast and energy-efficient manipulation of magnetic order in spintronic devices. To be deterministic, however, switching of perpendicularly magnetized materials by SOT requires a mechanism for in-plane symmetry breaking. Existing methods to do so involve the application of an in-plane bias magnetic field, or incorporation o... » read more

Factoring 2048-bit RSA Integers in 177 Days with 13 436 Qubits and a Multimode Memory

By Technical Paper Link - 18 Nov, 2021 - Comments: 0

Abstract: "We analyze the performance of a quantum computer architecture combining a small processor and a storage unit. By focusing on integer factorization, we show a reduction by several orders of magnitude of the number of processing qubits compared with a standard architecture using a planar grid of qubits with nearest-neighbor connectivity. This is achieved by taking advantage of a tem... » read more

← Older posts

tag: Université Paris-Saclay