Chip Industry Technical Paper Roundup: Sept. 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

LLMs In The High-Level Synthesis Design Flow


A new technical paper titled "Are LLMs Any Good for High-Level Synthesis?" was published by researchers at University of Arizona. Abstract "The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS proces... » read more

Chip Industry Technical Paper Roundup: August 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=249 /] More ReadingTechnical Paper Library home   » read more

Chip Industry Week in Review


Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

MTJ-Based CRAM Array


A new technical paper titled "Experimental demonstration of magnetic tunnel junction-based computational random-access memory" was published by researchers at University of Minnesota and University of Arizona, Tucson. Abstract "The conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence because ... » read more

Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Chip Industry’s Technical Paper Roundup: Dec 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=174 /] More ReadingTechnical Paper Library home » read more

How Different Metal Depositions Affect The Structure And Charge Transport Of 9-A Graphene Nanoribbons


A technical paper titled “Contact engineering for graphene nanoribbon devices” was published by researchers at University of Arizona, Swiss Federal Labs for Materials Science and Technology, University of California Berkeley, Stanford University, SRM Institute of Science and Technology, Texas A&M University, Lawrence Berkeley National Laboratory (LBNL), Max Planck Institute for Polymer... » read more

Chip Industry’s Technical Paper Roundup: July 12


New technical papers recently added to Semiconductor Engineering’s library: [table id=117 /] (more…) » read more

A Design Architecture For Optically Broadband Programmable PICs Utilizing Micromechanical Resonances 


A technical paper titled “Synchronous micromechanically resonant programmable photonic circuits” was published by researchers at The MITRE Corporation, Massachusetts Institute of Technology, Sandia National Laboratories, University of Arizona, and Brookhaven National Laboratory. Abstract: "Programmable photonic integrated circuits (PICs) are emerging as powerful tools for the precise ... » read more

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