Chip Industry Week in Review


Check out the Inside Chips podcast for our behind-the-scenes analysis of changes at Intel Foundry. Intel rolled out its updated process technology roadmap this week, along with early process design kit (PDK) for its 14A gate-all-around process technology. That node will utilize high-NA EUV, and include direct contact power delivery, the second generation of its backside power delivery techno... » read more

Research Bits: Feb. 4


High-power diamond transistors Researchers from the University of Glasgow, RMIT University, and Princeton University created a new diamond transistor for high-power electronics that remains switched off by default. The performance of the diamond was improved by coating it in hydrogen atoms followed by layers of aluminum oxide. “The challenge for power electronics is that the design of the... » read more

Chip Industry Week In Review


President Biden will raise the tariff rate on Chinese semiconductors from 25% to 50% by 2025, among other measures to protect U.S. businesses from China’s trade practices. Also, as part of President Biden’s AI Executive Order, the Administration released steps to protect workers from AI risks, including human oversight of systems and transparency about what systems are being used. Intel ... » read more

Chip Industry’s Technical Paper Roundup: October 9


New technical papers added to Semiconductor Engineering’s library this week. [table id=153 /] More Reading Technical Paper Library home » read more

Meeting The Material Challenges Of Nano-CMOS Electronics


A technical paper titled “Shockley-Read-Hall recombination and trap levels in In0.53 Ga0.47As point defects from first principles” was published by researchers at University of Glasgow and Synopsys Denmark. Abstract: "We present charge state transition levels of 23 intrinsic defects and dopant substitutions in the compound III-V semiconductor In0.53 Ga0.47 As, calculated with density func... » read more

Chip Industry’s Technical Paper Roundup: Sept 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=141 /] More Reading Technical Paper Library home » read more

Neuromorphic Artificial Synaptic Device Combining Memristor Arrays With Copper Iodide


A technical paper titled “Charge-Mediated Copper-Iodide-Based Artificial Synaptic Device with Ultrahigh Neuromorphic Efficacy” was published by researchers at University of Glasgow, City University of Hong Kong, and Hong Kong Metropolitan University. Abstract: "In the realm of artificial intelligence, ultrahigh-performance neuromorphic computing plays a significant role in executing multi... » read more

Technical Paper Round-Up: Aug 23


New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

DNN-Opt, A Novel Deep Neural Network (DNN) Based Black-Box Optimization Framework For Analog Sizing


This technical paper titled "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks" is co-authored from researchers at The University of Texas at Austin, Intel, University of Glasgow. The paper was a best paper candidate at DAC 2021. "In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizi... » read more

Technical Paper Round-up: August 8


New technical papers added to Semiconductor Engineering’s library this week. [table id=44 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

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