Chip Industry Week In Review


Europe's top court ruled in Intel's favor, voiding a $1.1 billion fine imposed by the European Union and dismissing charges of anti-competitive behavior. IBM released yield benchmarks for high-NA EUV, which serve as proof points that the newest advanced litho equipment will enable scaling beyond the 2nm process node. Also on the lithography front, Nikon is developing a maskless digital litho... » read more

Chip Industry Week In Review


Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

Research Bits: Mar. 11


Ferroelectric nanosheets Engineers from the University of Sydney, RMIT University, University of New South Wales, and University of Technology Sydney created a liquid metal alloy of tin, zirconium, and hafnium. The alloy has a thin oxide layer crust that enables it to be used to harvest ultra-thin tin oxide nanosheets doped with hafnium zirconium oxide, which could then be 2D printed on a subs... » read more

Chip Industry’s Technical Paper Roundup: Dec 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=174 /] More ReadingTechnical Paper Library home » read more

Lego-Like Photonics Chip With Expanded RF Bandwidth And Advanced Filter Control


A technical paper titled “Integrated microwave photonic notch filter using a heterogeneously integrated Brillouin and active-silicon photonic circuit” was published by researchers at University of Sydney and Australian National University. Abstract: "Microwave photonics (MWP) has unlocked a new paradigm for Radio Frequency (RF) signal processing by harnessing the inherent broadband and tu... » read more

Research Bits: December 5


Neuromorphic nanowires Researchers from UCLA and University of Sydney built an experimental computing system physically modeled after the biological brain. The device is composed of a tangled-up network of wires containing silver and selenium that were allowed to self-organize into a network of entangled nanowires on top of an array of 16 electrodes. The nanowire network physically reconfigure... » read more

Technical Paper Roundup: November 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=167 /] More Reading Technical Paper Library home » read more

Neuromorphic Devices Based On Memristive Nanowire Networks


A technical paper titled “Online dynamical learning and sequence memory with neuromorphic nanowire networks” was published by researchers at University of Sydney, University of California Los Angeles (UCLA), National Institute for Materials Science (NIMS), Kyushu Institute of Technology (Kyutech), and University of Sydney Nano Institute. Abstract: "Nanowire Networks (NWNs) belong to an em... » read more

Chip Industry’s Technical Paper Roundup: July 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=119 /] More Reading Technical Paper Library home » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership


A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

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