Chip Industry’s Technical Paper Roundup: July 24

Flip-chip with photodiode; protecting NoC against reverse engineering attack; DRAM-based multi-level PIM; AI supercomputer for LLM; accelerator for homomorphic library; gallium oxide flash memory; topological semimetal; 3D MEMS coaxial socket; on-chip learning circuit in SNN; 2D molybdenum disulfide.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes University of Toronto, Alphawave IP, and Huawei Technologies Canada
ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks University of Florida
Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc.
Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models University of Washington and University of Sydney
VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library University of Pisa
Demonstration of β-Ga2O3 nonvolatile flash memory for oxide electronics King Abdullah University of Science and Technology (KAUST) and Indian Institute of Technology
Robust negative longitudinal magnetoresistance and spin-orbit torque in sputtered Pt3Sn and Pt3SnxFe1-x topological semimetal University of Minnesota
Fabrication and Characterization of Three-Dimensional Microelectromechanical System Coaxial Socket Device for Semiconductor Package Testing Yonsei University and Protec MEMS Technology
Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks Institute of Neuroinformatics, University of Zurich, and ETH Zurich
Toolbox of Advanced Atomic Layer Deposition Processes for Tailoring Large-Area MoS2 Thin Films at 150 °C Eindhoven University of Technology, University of Michigan, and University College Cork

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