tag: UPF

There Can Be Only One
By Synopsys - 14 Mar, 2013 - Comments: 0

By Cary Chin The tagline of the 1986 fantasy film “Highlander” implies that, at least in some instances, we eventually will arrive at a single, best solution for our problems. In the case of low-power design, the most obvious application of the phrase is in the standardization of low power intent formats, where the Unified Power Format (UPF) and the Common Power Format (CPF) have been lock... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Unified Power Intent
By Ed Sperling - 01 Mar, 2013 - Comments: 0

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format. For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the... » read more

The Next UPF
By Erich Marschner - 06 Dec, 2012 - Comments: 0

By Erich Marschner If all goes according to schedule, the new version (2.1) of five-year-old Unified Power Format (UPF) standard will be approved by the IEEE early next year. This is good news, because in the five years since UPF was first defined the demand for systems with both longer battery life and more functionality has increased significantly. As just one example: according to Gartner, ... » read more

Tech Talk: LP Design And Verification
By Ed Sperling - 06 Dec, 2012 - Comments: 0

Cadence's Qi Wang talks with Low-Power/High-Performance Engineering about power formats and what else can be done to save power in SoCs. [youtube vid=afJ6VQ0AYgg] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

More Intelligent Standards
By Ed Sperling - 11 Oct, 2012 - Comments: 0

There is a lot of talk these days about holistic power intent. The terminology may sound new, but the underpinnings are not. This was the idea behind the Common Power Format, which was proposed by Cadence back in 2006, and the Unified Power Format (more recently known as IEEE 1801), which was introduced the following year. These ideas were forward-looking at the time. They grasped the growi... » read more

Power Mode And State
By Luke Lang - 12 Jul, 2012 - Comments: 0

By Luke Lang Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state. In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power ... » read more

LP Macros 2
By Luke Lang - 14 Jun, 2012 - Comments: 0

By Luke Lang Last month, I compared the CPF macro model with LP attributes in the Liberty model. The CPF macro model was developed when Liberty had very little LP attributes to support LP designs. Even today, Liberty still lacks LP attributes to describe some of the common power intent in LP designs. One example is an LP IP block with internal power switches and shutoff domains. Because mos... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

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