tag: UPF

Power Intent Formats: Power Domain
By Luke Lang - 06 Oct, 2011 - Comments: 0

By Luke Lang Starting this month, I will be writing a series of blogs inspired by “Dueling Power Formats”. The article correctly points out that there are currently three power formats: CPF, UPF 1.0, and IEEE 1801. Some designers will find themselves in a position of having to choose a format. Others will need to work with both formats. Regardless of which position one is in, these LP desi... » read more

Dueling Power Formats
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

The Pain of UPF/CPF
By Ann Mutschler - 10 Feb, 2011 - Comments: 0

Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats. According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code. Because they are learning these ... » read more

The Power Of Standards
By Barry Pangrle - 08 Jul, 2010 - Comments: 0

By Barry Pangrle It’s often said that the wonderful thing about standards is that there are so many to choose from. As an industry, EDA seems to have a short memory as VMM and OVM (now becoming UVM), VHDL and Verilog, and more recently UPF and CPF. In cases where one standard suffices, it is horribly inefficient to create multiple “standards.” It is a waste of effort and resources for ED... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

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