So Many Waivers Hiding Issues

By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric

By Progyna Khondkar - 13 Sep, 2018 - Comments: 0

Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

UPF-Aware Clock-Domain Crossing

By Ed Sperling - 29 Aug, 2018 - Comments: 0

Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Agile Standards

By Brian Bailey - 08 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down with Lu Dai, chairman for Accellera and senior director of engineering at Qualcomm, to discuss what's changing in standards development. What follows are excerpts of that conversation. SE: Accellera has had a great first half of the year. Dai: Yes, we are only half way through the year and yet we got Portable Stimulus Standard (PSS) out, the SystemC CCI ... » read more

Debug Issues Grow At New Nodes

By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

Power-Aware Static Checks: Static Checker Results And Debugging Techniques

By Progyna Khondkar - 17 Jul, 2018 - Comments: 0

In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

Three Steps To Low Power Coverage Closure

By Awashesh Kumar - 18 Jun, 2018 - Comments: 0

By Awashesh Kumar and Madhur Bhargava Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these elements at a high abstraction level. However, power-aware coverage closure is difficult to attain and complex by nature. Existing low-power coverage methodo... » read more

Tech Talk: Improving Verification

By Ann Mutschler - 26 Apr, 2018 - Comments: 0

Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Power Aware Intent And Structural Verification Of Low-Power Designs

By Progyna Khondkar - 08 Mar, 2018 - Comments: 3

Power aware static verification, more popularly known as PA-Static checks, is performed on designs that adopt certain power dissipation reduction techniques through the power intent or [gettech id="31044" t_name="UPF"]. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requiremen... » read more

IP And Power

By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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Partitioning In The Chiplet Era

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NAND Flash Targets 1,000 Layers

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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