The Week In Review: Design/IoT

By Jesse Allen - 07 Aug, 2015 - Comments: 0

Tools Cadence unveiled Joules, its new RTL power analysis solution. The tool performs design synthesis using a new integrated prototype mode of Cadence's Genus Synthesis product, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. IP Synopsys and ASMedia completed a successful interoperability demonstration of Synopsys' USB 3.1 Devi... » read more

USB Connectors Get Smarter

By Ann Mutschler - 30 Jul, 2015 - Comments: 0

By now, there’s quite a buzz about the new USB Type-C spec given that it provides for a reversible plug connector for USB devices and cabling, aiming to end the endless cable flipping to make sure the orientation is correction. To avoid confusion, while developed at about the same time as the USB 3.1 specification, it is distinct from that one. When it comes to software support for Type-C,... » read more

The Week In Review: Design

By Ed Sperling - 31 Oct, 2014 - Comments: 0

Tools Mentor Graphics rolled out an extension to its PCB design platform that allows for synchronization of processes across multi-board systems. The new tool captures logic and system definitions for boards, cables, backplanes, cable assemblies, sensors and actuators. Cadence introduced a dynamic characterization solution for mixed signal blocks such as PLLs, data converters, high-speed tr... » read more

USB 3.1: Evolution And Revolution

By Various Writers - 12 Mar, 2014 - Comments: 0

USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defi... » read more

Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates

By Matthew Myers - 16 Jan, 2014 - Comments: 0

In January 2013, the USB-IF announced USB 3.1, a new generation of the protocol that will double USB 3.0 data throughput performance to 10 Gbps. In addition to this increased speed, the specification requires compatibility with existing cables, connectors, software stacks, and device class protocols. USB 3.1 products must support existing 5 Gbps and new 10 Gbps hubs and devices, as well as olde... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.