tag: validation

Synopsys SoundWire Test Suite
By Synopsys - 08 Mar, 2017 - Comments: 0

Validation and interoperability are always a challenge for any new protocol. An earlier white paper, Digital Audio Simplified: MIPI SoundWire, discussed the basics of digital audio transmission, and benefits of SoundWire over other audio interfaces. This whitepaper describes how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite. To read more, cli... » read more

Quality Issues Widen
By Ed Sperling - 06 Mar, 2017 - Comments: 0

As the amount of semiconductor content in cars, medical and industrial applications increases, so does the concern about how long these devices will function properly—and what exactly that means. Quality is frequently a fuzzy concept. In mobile phones, problems have ranged from bad antenna placement, which resulted in batteries draining too quickly, to features that take too long to load. ... » read more

Ensure Robust Encryption With CAVP Validation For FIPS 140-2 Conformance
By Derek Bouius - 08 Dec, 2016 - Comments: 0

Cryptographic algorithms are mathematical procedures used to implement security protocols in today’s devices and communication infrastructure. Designers must validate their cryptographic algorithm implementations through certification by regulatory bodies, such as Communications Security Establishment Canada (CSEC) and National Institute of Standards and Technology (NIST), to ensure accuracy ... » read more

Power Options And Issues
By Ann Mutschler - 08 Sep, 2016 - Comments: 0

In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Connected Reliability Concerns
By Ed Sperling - 04 Aug, 2016 - Comments: 0

Ever since the invention of the integrated circuit, the focus has been on improving technology—making it faster, smaller, cheaper, while also cutting the power budget. With the advent of the IoT and ubiquitous connectivity, the value proposition will change. Rather than just improving the chip, the focus will shift to how that chip behaves in context. How does it work in a connected world... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Managing Validation And Verification Abstract Activities For DO-254
By Aldec - 24 Feb, 2016 - Comments: 0

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

The Beginning
By Anupam Bakshi - 22 Dec, 2015 - Comments: 0

We all want our creations to transcend time. Our products, our designs—even our specifications. Specifications are more than just ideas or collections of requirements or static collections of implementation details. They live inside many chips and many designs, and the more flexible and portable they are, the longer they remain relevant. End devices may be replaced relatively quickly, but ... » read more

IP Design Essentials For Reliability And SoC Integration
By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

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