tag: validation

Engineering Challenges for Viable Autonomous Vehicles
By Mentor, a Siemens Business - 02 May, 2018 - Comments: 0

The rise of autonomous and electric vehicles brings with it a host of engineering implications, including an increase in the number and variety of sensors in the vehicle, increasing software and hardware complexity, massive validation and verification cycles, heightened safety and security requirements, and new demands for digital data continuity. This paper is an overview of how six interdisci... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification
By James Paris - 26 Apr, 2018 - Comments: 0

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

Verification And Validation Brothers
By Brian Bailey - 22 Mar, 2018 - Comments: 0

At DVCon this year, Doug Amos took the stage for the [getentity id="22017" e_name="Mentor, a Siemens Business"] sponsored lunch presentation. For those of you who were there but decided to skip the lunch, expecting the traditional forced sales pitch, you made a mistake. Amos is one of those rare people who know how to inject humor, teaching and marketing into a single presentation such that the... » read more

Merging Verification With Validation
By Brian Bailey - 22 Mar, 2018 - Comments: 3

Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs
By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Co-modeling: A Powerful Capability For Hardware Emulation
By Mentor, a Siemens Business - 13 Dec, 2017 - Comments: 0

Understanding co-modeling technology, its impact on verification and validation should be a critical aim for anyone selecting and deploying emulation co-modeling resources. This paper explores how emulation co-modeling — specifically for the Veloce Strato emulation platform from Mentor, a Siemens business — is architected to meet the needs of advanced verification and validation. To rea... » read more

The Chiplet Option
By Ed Sperling - 09 Oct, 2017 - Comments: 0

All of the leading chipmakers, foundries and OSATs are now working with some sort of advanced packaging. The next step is to add some consistency to those efforts to be able to assemble chips much more quickly and inexpensively. DARPA has been promoting chiplets as the best way to solve this problem, and for the military, this is a pretty logical choice. With a push toward heterogeneity in c... » read more

Verifying AI, Machine Learning
By Ed Sperling - 28 Sep, 2017 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

Are You Designing The Right Product?
By Malte Doerper - 28 Aug, 2017 - Comments: 0

Development and production of SoCs is becoming more and more complex and expensive. And rightfully so, the semiconductor industry spends billions of dollars on verification efforts. Verification is about checking the design behaves per its specification, a process that is very important and well understood. Still, something can go terribly wrong because having a verified SoC does not guarant... » read more

Verification And Validation Don’t Mean The Same Thing
By Tom De Schutter - 25 May, 2017 - Comments: 0

While often used intermixed, verification and validation are quite different procedures with different goals and different means to achieve those goals. No better way to clear up the confusion by starting with some definitions as stated by Wikipedia, https://en.wikipedia.org/wiki/Verification_and_validation: “Verification is intended to check that a product, service, or system (or porti... » read more

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