tag: validation

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Unifying Hardware-Assisted Verification And Validation Using UVM And Emulation
By Various Writers - 25 Jul, 2013 - Comments: 0

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validatio... » read more

Unifying Hardware-Assisted Verification And Validation Using UVM And Emulation
By Various Writers - 25 Jul, 2013 - Comments: 0

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validatio... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

Engineering’s Growing Blacklist
By Ed Sperling - 25 Mar, 2011 - Comments: 0

The number of system-level design flaws is rising, and they’re not just little mistakes. These are high-profile errors that are making headlines all over the globe. While it’s debatable whether Toyota’s problem was a hardware or software design glitch, the simple fact is there was a design flaw somewhere. That’s true for the BP Gulf of Mexico leak, regardless of who’s responsible f... » read more

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