tag: Veeco Instruments

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 16 Oct, 2020 - Comments: 0

Security Intel announced new security features for its code-named Ice Lake CPU, according to a story in SecurityWeek. The 10nm-based Xeon Scalable will have SGX trusted execution environment and several new features for memory encryption, firmware resilience, and cryptographic performance acceleration. The new Total Memory Encryption (TME) feature in the CPU will encrypt access to memory. S... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 02 Jul, 2020 - Comments: 0

The American Foundries Act, a bipartisan initiative to revive U.S. leadership in the global microelectronics sector, was announced by U.S. Democratic Senator Chuck Schumer from New York. “The economic and national security risks posed by relying too heavily on foreign semiconductor suppliers cannot be ignored, and Upstate New York, which has a robust semiconductor sector, is the perfect place... » read more

Effective Post-TSV-DRIE Wet Clean Process For Through Silicon Via Applications
By Veeco - 18 Mar, 2020 - Comments: 0

Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 07 Feb, 2020 - Comments: 0

Internet of Things SEMI-FlexTech launched six flexible hybrid electronics (FHE) projects, collaborating with U.S. Army Research Laboratory (ARL), to accelerate innovations in sensor and sensor systems. Participating in the projects are American Semiconductor, Inc., University of Texas El Paso, Tekscan, PARC, Alertgy, and Iowa State University, among others. Some of the projects include develop... » read more

Accelerating Silicon Carbide Power Electronics Devices Into High Volume Manufacturing With Mechanical Dicing System
By Veeco - 16 Dec, 2019 - Comments: 0

Silicon carbide (SiC) is a wideband gap semiconductor material that has huge potential to enrich our lives by enabling better technology with improved connectivity and efficiency. It offers many advantages over common silicon (Si) for power applications as it can be doped much higher than silicon to achieve optimal blocking voltage. In addition, SiC high thermal conductivity characteristic enab... » read more

Process To Produce High Aspect Ratio Electroplated Copper Pillars On 300 mm Wafers
By Veeco - 16 Oct, 2019 - Comments: 0

This work provides details of a complete and partially optimized process to manufacture high aspect ratio copper pillars with heights of up to 80 µm on 200 and 300 mm wafers. Across wafer uniformity data for all materials and process steps are given. Results will show excellent resist adhesion on copper and electroplating durability. Cross sectional SEM analysis of resist and electroplated pil... » read more

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology
By Veeco - 18 Sep, 2019 - Comments: 0

Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

Intra-Field Stress Impact on Global Wafer Deformation
By Veeco - 14 Aug, 2019 - Comments: 0

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane disto... » read more

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