tag: Veeco

Week In Review: Manufacturing, Test
By Mark LaPedus - 03 Jan, 2020 - Comments: 0

Market research The worldwide semiconductor market is forecast to reach $409 billion in 2019, down 12.8% over 2018, according to the World Semiconductor Trade Statistics (WSTS) organization. Memory fell by 33.0% in 2019, while analog dropped 7.9% and logic declined by 4.3%, according to the WSTS. In 2020, the IC market is expected to recover and grow by 5.9%, according to the WSTS. Optoelec... » read more

What’s Next For High Bandwidth Memory
By Mark LaPedus - 17 Dec, 2019 - Comments: 1

A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

Accelerating Silicon Carbide Power Electronics Devices Into High Volume Manufacturing With Mechanical Dicing System
By Veeco - 16 Dec, 2019 - Comments: 0

Silicon carbide (SiC) is a wideband gap semiconductor material that has huge potential to enrich our lives by enabling better technology with improved connectivity and efficiency. It offers many advantages over common silicon (Si) for power applications as it can be doped much higher than silicon to achieve optimal blocking voltage. In addition, SiC high thermal conductivity characteristic enab... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 08 Nov, 2019 - Comments: 0

Chipmakers The IC industry once had several leading-edge vendors that invested and built new fabs. But over time, the field has narrowed due to soaring costs and a dwindling customer base. In 1994, the share of semiconductor industry capital spending held by the top five companies was 25%, according to IC Insights. This meant that a number of companies invested and built new fabs during the... » read more

Making Random Variation Less Random
By Ed Sperling - 21 Oct, 2019 - Comments: 0

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Process To Produce High Aspect Ratio Electroplated Copper Pillars On 300 mm Wafers
By Veeco - 16 Oct, 2019 - Comments: 0

This work provides details of a complete and partially optimized process to manufacture high aspect ratio copper pillars with heights of up to 80 µm on 200 and 300 mm wafers. Across wafer uniformity data for all materials and process steps are given. Results will show excellent resist adhesion on copper and electroplating durability. Cross sectional SEM analysis of resist and electroplated pil... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

External Resistance Reduction By Nanosecond Laser Anneal In Si/SiGe CMOS Technology
By Veeco - 18 Sep, 2019 - Comments: 0

Authors: 1Oleg Gluschenkov, 1Heng Wu, 1Kevin Brew, 2Chengyu Niu, 1Lan Yu, 1Yasir Sulehria, 1Samuel Choi, 22Curtis Durfee, 1James Demarest, 1Adra Carr, 3Shaoyin Chen, 3Jim Willis, 3Thirumal Thanigaivelan, 1Fee-li Lie, 2Walter Kleemeier, and 1Dechao Guo 1IBM Research, 257 Fuller Road, Albany, NY 12203, USA, email: [email protected] 2GLOBALFOUNDRIES Inc., Albany, NY, USA, 3ULTRATECH, a division ... » read more

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