tag: verification

Benchmark and Evaluation Framework For Characterizing LLM Performance In Formal Verification (UC Berkeley, Nvidia)
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware" was published by researchers at UC Berkeley and NVIDIA. Abstract "The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital chip design. In particula... » read more

Pre-Silicon Verification Method Addressing Critical Aspects of Speculative Execution Vulnerability Detection
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection" was published by researchers at Technical University of Darmstadt and Texas A&M University. "We introduce Specure, a novel pre-silicon verification method composing hardware fuzzing with Information Flow Tracking (IFT) to address speculative execution leakages. Integrating IFT enables two... » read more

RISC-V Conformance
By Brian Bailey - 31 Oct, 2024 - Comments: 0

Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is conformance, which must exist before software portability becomes possible. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO... » read more

The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
By Pavani Jella - 24 Oct, 2024 - Comments: 0

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in t... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

New Challenges In IC Reliability
By Ed Sperling - 15 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

Maximizing Coverage Metrics with Formal Unreachability Analysis
By Synopsys - 25 Sep, 2024 - Comments: 0

Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

Simulation Replay Tackles Key Verification Challenges
By Robert Ruiz - 12 Sep, 2024 - Comments: 0

Simulation lies at the heart of both verification and pre-silicon validation for every semiconductor development project. Finding functional or power problems in the bringup lab is much too late, leading to very expensive chip turns. Thorough simulation before tapeout, coupled with comprehensive coverage metrics, is the only way to avoid surprises in silicon. However, the enormous size and comp... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)
By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

Managing Complexity And A Left Shift: Reconfigurable Mixed-Signal Circuits For Complex Integrated Systems
By Bjorn Zeugmann - 08 Aug, 2024 - Comments: 0

By Björn Zeugmann and Benjamin Prautsch The chip market is growing worldwide; it’s projected to nearly double by 2030 to over one trillion dollars. Most of this market is made up of digital functions in the form of logic, microprocessors, and memory. Although analog ICs account for only around 15% of the total, they are key components for overall systems and are therefore almost always pr... » read more

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