tag: verification

HyperLynx
By Siemens EDA - 03 Apr, 2025 - Comments: 0

You gain the full power of HyperLynx when it is fully integrated as part of the Xpedition PCB design flow. Yet, it also interfaces with most PCB layout tools, allowing any engineer to quickly import and set up their PCB designs for analysis, regardless of their existing toolset. And because its progressive verification methodology analyzes a design in stages, HyperLynx locates issues earlier an... » read more

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)
By Technical Paper Link - 01 Apr, 2025 - Comments: 0

A new technical paper titled "ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification" was published by researchers at University of Florida. Abstract "Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scale with increasing ... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck
By Harry Foster - 27 Mar, 2025 - Comments: 0

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

First-Time Silicon Success Plummets
By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

Digital Twins For Design And Verification Workflows
By Brian Bailey - 27 Mar, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior d... » read more

The Evolving Role Of AI In Verification
By Ann Mutschler - 26 Mar, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure the functional correctness of devices has increased exponentially as chips have gotten more complex and evolved into SoC, 3D-ICs, multi-die chiplets and beyond. Semiconductor Engineering sat down with a panel of experts, which included Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group dir... » read more

New Innovative Way To Functionally Verify Heterogeneous 2D/3D Package Connectivity
By Siemens EDA - 12 Mar, 2025 - Comments: 0

Historically, IC package design has been a relatively simple task which allowed the die bumps to be fanned out to a geometry suitable for connecting to a printed circuit board. The package netlist was often captured by the package designer, typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection. Modern package and interpos... » read more

Shift-Left Pattern Matching Boosts Automotive IC Quality And Time-To-Market
By John Muirhead - 06 Mar, 2025 - Comments: 0

As the automotive industry races towards a future of connected, autonomous, and electrified vehicles, the complexity of integrated circuits (ICs) powering these innovations is reaching unprecedented levels. Modern automotive ICs incorporate a diverse mix of custom and third-party intellectual property (IP), each with unique performance requirements that must be meticulously verified to ensure f... » read more

Shift Left With Calibre Pattern Matching
By Siemens EDA - 06 Mar, 2025 - Comments: 0

As integrated circuit (IC) designs become increasingly complex, early-stage verification is crucial to ensure productivity and quality in design processes. The "shift left" verification approach, enabled by Siemens’ Calibre nmPlatform, helps IC design teams to identify and resolve critical issues much earlier in the design cycle. As part of the shift left platform, Calibre Pattern Matching... » read more

Scenario Coverage In Formal Verification
By Ed Sperling - 05 Mar, 2025 - Comments: 0

A rapid increase in complexity with heterogeneous assemblies and advanced-node chips is raising all sorts of questions on the formal verification side about the completeness of coverage. Engineers may assume proofs are complete, but in many cases they're black boxes that provide little or no insights into what's actually being proven. This is where scenario coverage comes into play. Ashish Darb... » read more

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