tag: verification

Beyond Simulation: Transforming Early IC Design With Insight Analyzer
By Siemens EDA - 13 Feb, 2025 - Comments: 0

Traditional verification methods are proving inadequate for addressing critical reliability challenges in today's increasingly complex integrated circuit (IC) designs. Modern IC design requires a proactive approach to verification that emphasizes early-stage analysis. The shift-left methodology enables earlier identification of potential design risks, addressing the complex challenges of IP blo... » read more

Enhancing Reliability For Automotive ICs
By Matthew Hogan - 06 Feb, 2025 - Comments: 0

As an IC designer focused on automotive applications, reliability is likely one of your top priorities. The components you develop need to withstand extreme environmental conditions, maintain performance over extended lifetimes, and meet rigorous industry standards. Failure is simply not an option when it comes to automotive electronics. Achieving the required levels of reliability can be a ... » read more

Beyond Simulation: Transforming Early IC Design With Insight Analyzer
By Siemens EDA - 06 Feb, 2025 - Comments: 0

Traditional verification methods are proving inadequate for addressing critical reliability challenges in today's increasingly complex integrated circuit (IC) designs. Modern IC design requires a proactive approach to verification that emphasizes early-stage analysis. The shift-left methodology enables earlier identification of potential design risks, addressing the complex challenges of IP blo... » read more

What’s Missing From Predictions
By Brian Bailey - 30 Jan, 2025 - Comments: 1

At this point everyone has made their predictions for the year, but there is one thing many people get wrong. Predictions are not about innovation. They are about pain and what is causing it. This industry is risk-averse, and everyone wants to continue doing what they are doing. But there comes a point when it's so painful to continue that something has to change. Having something that is... » read more

Complete Transistor Level Electrical Checks With Formal Analysis
By Almitra Pradhan - 30 Jan, 2025 - Comments: 0

Nothing is worse for a design team than a chip that fails to work in the bringup lab. Electrical problems are historically a major cause of such failures. Power leaks, power-ground DC paths, missing level shifters, and design flaws such as high fanout lead to unexpected power consumption, incorrect functionality, and even total meltdown. Designers learned years ago that pre-silicon electrical c... » read more

Microsoft Accelerates DRC With Shift-Left Verification
By Siemens EDA - 30 Jan, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

EDA Revenue Hit Record High In Q3
By Ed Sperling - 14 Jan, 2025 - Comments: 0

EDA and IP revenue increased 8.8% in Q3 2024, dragged down from the double-digit growth of recent quarters by a softening in sales to China, according to the most recent report by SEMI. For more than a decade, China's growth propped up the entire tools industry, reporting consistent double-digit growth growth that reached as high as 40% quarter over quarter. But with ongoing trade restrictio... » read more

Design And Verification Issues In 2024
By Brian Bailey - 19 Dec, 2024 - Comments: 0

At the end of each year, I look back over the stories published and those that top the charts in terms of readership. I concentrate on those stories that are about the EDA tools and flows and the factors that are influencing them. These are good indicators of the problems designers and verification teams are facing today, and where they are looking for answers. This year's leading categories... » read more

Improving Verification Performance
By Brian Bailey - 19 Dec, 2024 - Comments: 0

Without methodology improvements, verification teams would not be able keep up with the growing complexity and breadth of the tasks assigned to them. Tools alone will not provide the answer. The magnitude of the verification task continues to outpace the tools, forcing design teams to seek out better ways to intermix and utilize the tools that are available. But as verification teams take on... » read more

RISC-V Profiles Help Conformance
By Brian Bailey - 18 Dec, 2024 - Comments: 0

Experts At The Table: What's needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeist... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy