tag: verification

Abstractions: The Good, Bad And Ugly
By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Design And Verification Survey Results
By Graham Bell - 27 Feb, 2014 - Comments: 1

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

Does It Take A Catastrophe?
By Linda Prowse Fosler - 20 Feb, 2014 - Comments: 0

What makes a company search for new verification methods and tools? Sometimes organizations change, proactively, because they are wise and want to avoid problems; but sadly, more often it is a catastrophe that forces change. This was the case with a large U.S. supplier of safety-critical and high-reliability ICs. After a failed chip, it finally moved from simply verifying the analog and digi... » read more

Executive Insight: Kathryn Kranen
By Ed Sperling - 17 Feb, 2014 - Comments: 0

Semiconductor Engineering sat down with Kathryn Kranen, president and CEO of Jasper Design Automation, to discuss what's changing in the semiconductor industry, why that's happening, and what to watch out for. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you up at night? Kranen: Figuring out ways to... » read more

Do Chips Really Work The First Time?
By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
By Karthik Srinivasan - 13 Feb, 2014 - Comments: 0

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

The Growing Verification Challenge
By Ed Sperling - 30 Jan, 2014 - Comments: 1

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

Billion-Gate Signoff
By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

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