Digitizing Memory Design And Verification To Accelerate Development Turnaround Time

By Anand Thiruvengadam - 10 Oct, 2022 - Comments: 0

By Anand Thiruvengadam, Farzin Rasteh, Preeti Jain, and Jim Schultz Some digital design and verification engineers imagine that their colleagues working on analog/mixed-signal (AMS) chips are jealous. After all, the digital development flow has enjoyed the benefits of increased automation and higher levels of abstraction for many years. Hand-instantiated devices and manual interconnection we... » read more

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

By Tom Fitzpatrick - 04 Oct, 2022 - Comments: 0

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Verification Methodologies Evolve, But Slowly

By Brian Bailey - 29 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Can ML Help Verification? Maybe

By Brian Bailey - 22 Sep, 2022 - Comments: 0

Functional verification produces an enormous amount of data that could be used to train a machine learning system, but it's not always clear which data is useful or whether it can help. The challenge with ML is understanding when and where to use it, and how to integrate it with other tools and approaches. With a big enough hammer, it is tempting to call everything a nail, and just throwing ... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs

By Siemens EDA - 22 Sep, 2022 - Comments: 0

Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

Efficient Verification Of Mixed-Signal Series IP Using UVM

By Cadence - 21 Sep, 2022 - Comments: 0

Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal ... » read more

Recipe To Catch Bugs Faster Using Machine Learning

By Anika Sunda - 19 Sep, 2022 - Comments: 0

We all agree that verification and debug take up a significant amount of time and are arguably the most challenging parts of chip development. Simulator performance has consistently topped the charts and is a critical component in the verification process. Still, the need of the hour is to stretch beyond simulator speed to achieve maximum verification throughput and efficiency. Artificial in... » read more

How Mature Are Verification Methodologies?

By Brian Bailey - 14 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

New Processor Fuzzing Mechanism

By Technical Paper Link - 07 Sep, 2022 - Comments: 0

Researchers from Boston University and University of Washington published a technical paper titled "ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers." Abstract "As the complexity of modern processors has increased over the years, developing effective verification strategies to identify bugs prior to manufacturing has become critical. Undiscovered micro-architectur... » read more

Better, Faster, And More Efficient Verification With The Power Of AI

By Synopsys - 07 Sep, 2022 - Comments: 0

Verification is often the most challenging part of the chip development process. Verification engineers have to balance quality of results (QOR) with time to results (TTR) and cost of results (COR). AI and ML technologies can play a significant part in increasing QOR, speeding up TTR, and reducing COR. This white paper outlines some of the major challenges for verification, describes how AI pro... » read more

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tag: verification

Digitizing Memory Design And Verification To Accelerate Development Turnaround Time

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

Verification Methodologies Evolve, But Slowly

Can ML Help Verification? Maybe

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs

Efficient Verification Of Mixed-Signal Series IP Using UVM

Recipe To Catch Bugs Faster Using Machine Learning

How Mature Are Verification Methodologies?

New Processor Fuzzing Mechanism

Better, Faster, And More Efficient Verification With The Power Of AI

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