tag: verification

Bug Hunt! Spiraling In On Formal Coverage Closure
By Mark Eslinger - 13 Jan, 2022 - Comments: 0

By Mark Eslinger and Jin Hou Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging as an efficient verification approach. Although formal verification will not handle the complexity of a design at the SoC level, it is an efficient tool to verify th... » read more

Traceability, Unfamiliar But Critical
By Paul Graykowski - 06 Jan, 2022 - Comments: 0

Many understand that traceability is a popular concept. Still, understanding traceability in detail is more challenging, especially in how it connects to familiar objectives in the semiconductor design space. A simple way to understand is this: When a customer (call them C) asks a semiconductor supplier (call them S) to build a device to meet a system objective, they provide S with specificatio... » read more

Domain-Specific Design Drives EDA Changes
By Ann Mutschler - 03 Jan, 2022 - Comments: 0

The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

Reliability Concerns Shift Left Into Chip Design
By Ann Mutschler - 22 Dec, 2021 - Comments: 1

Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

The Third Generation Of FPGA Prototyping
By Robert Parris - 22 Dec, 2021 - Comments: 0

Bench setups with physical prototypes lie at the very heart of electrical and electronic engineering. With all due respect to the many powerful forms of modeling and simulation, at some point the engineering team wants to work with hardware. When a system is built entirely from existing components, it is possible to build a prototype of the product as soon as it has been designed. When the desi... » read more

Taking 2.5D/3DIC Physical Verification To The Next Level
By Siemens EDA - 21 Dec, 2021 - Comments: 0

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DSTACK precheck mode enables design teams to find and correct basic implementation mistakes ... » read more

The Return Of DAC In-Person
By Brian Bailey - 15 Dec, 2021 - Comments: 0

Apart from masked faces everywhere, you could be excused for not knowing that there was a pandemic going on. Sure, the numbers were down, the show floor was smaller, and most of the parties didn't happen, but everyone was so happy to be able to bump elbows with their colleagues. Buttons were available for attendees to show the level of comfort they had with various types of greetings, from "... » read more

Veloce Prototyping Solutions Accelerate Verification Of HPC AI-Enabled SoCs
By Siemens EDA - 08 Dec, 2021 - Comments: 0

This white paper goes through the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design. The starting point in the journey explores the use cases for designs illustrating the impact HPC AI-enabled systems and resources have on o... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

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