What’s Next For Emulation

By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Debug Solutions For Designers Accelerate Time To Verification

By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

Intelligent Coverage Optimization: Verification Closure In Hyperdrive

By Anika Malhotra - 28 Oct, 2021 - Comments: 0

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when automated stimulus generation techniques are used. All modern hardware design and verification languages include constructs for functional coverage specification and support a range of structural coverag... » read more

The Road To Osmosis

By Rob van Blommestein - 27 Oct, 2021 - Comments: 0

It’s happening. Some may have speculated that, with the acquisition of OneSpin by Siemens, the OneSpin user group meeting, more commonly known as Osmosis, would be formally (pun intended) absorbed into a larger Siemens event. Well, I’m here to tell you that Osmosis is officially on the books and will continue to focus on the specific area of formal verification. The team has been working di... » read more

Leveraging Symbolic Simulations For IO Verification

By Moninder Singh - 14 Oct, 2021 - Comments: 0

IO libraries and interface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Interface IPs are the literal gatekeepers to the flow of logical and electrical information from one IC to another to form today’s complex computer systems, influencing almost every aspect of our lives these days. Interface IPs (e... » read more

Using IP-XACT To Solve Design And Verification Problems

By Anika Malhotra - 13 Oct, 2021 - Comments: 0

As today’s SoC designs grow more complex and time-to-market (TTM) pressures rise, designers are looking for techniques to build and update designs easily. Key elements for addressing these SoC challenges include the incorporation of more commercial IP components, internal design IP reuse, and extensive automation of design and verification activities. Enhanced interoperability and reusability... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization

By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

Containing The Explosion In Data

By Brian Bailey - 23 Sep, 2021 - Comments: 0

The amount of data that could be kept for every design is gargantuan, but even that may not be enough these days as lifecycle management, continuous verification, regulatory requirements, and globalization add to the data that needs to be stored. But data has no value if it cannot be found or used in ways that provide more benefit than the cost of storing it. "Data management is not unique t... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs

By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

The Shortest Path Deception

By Derong Yan - 09 Sep, 2021 - Comments: 1

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

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tag: verification

What’s Next For Emulation

Debug Solutions For Designers Accelerate Time To Verification

Intelligent Coverage Optimization: Verification Closure In Hyperdrive

The Road To Osmosis

Leveraging Symbolic Simulations For IO Verification

Using IP-XACT To Solve Design And Verification Problems

Accelerating Verification Shift Left With Intelligent Coverage Optimization

Containing The Explosion In Data

Automated ESD Protection Verification For 2.5D And 3D ICs

The Shortest Path Deception

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