tag: verification

Veloce Prototyping Solutions Accelerate Verification Of HPC AI-Enabled SoCs
By Siemens EDA - 08 Dec, 2021 - Comments: 0

This white paper goes through the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design. The starting point in the journey explores the use cases for designs illustrating the impact HPC AI-enabled systems and resources have on o... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Improving Predictability Through Design Solutions Methodologies
By Rusty Stuber - 23 Nov, 2021 - Comments: 0

“Plans are useless, but planning is indispensable.” – Dwight D. Eisenhower Our first article called for the need to change how we think about verification. In this follow-up, we dive deeper into the tools needed for today’s verification. Project milestones are destined to move. Development estimates are rough and almost always optimistic. Each development stage contains interdepe... » read more

AKER: A Design and Verification Framework for Safe and Secure SoC Access Control
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP cores have concurrent access to on-chip shared resources. In security-critical applications, IP cores have different privilege levels for accessing shared resources, which must be regulated by an access control system. AKER is a design and verification framework for SoC access control. AKER builds ... » read more

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Over the last few decades, the cost and difficulty of producing integrated circuits at ever shrinking node sizes has vastly increased, resulting in the manufacturing sector moving overseas. Using offshore foundries for chip fabrication, however, introduces new vulnerabilities into the design flow since there is little to no observability into the manufacturing process. At the same ... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

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