tag: verification

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

Next Challenge: Known Good Systems
By Ed Sperling - 07 Jul, 2020 - Comments: 0

The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge. This doesn't mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme t... » read more

Variables Complicate Safety-Critical Device Verification
By Ann Mutschler - 01 Jul, 2020 - Comments: 0

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Gaps Emerging In System Integration
By Brian Bailey - 29 Jun, 2020 - Comments: 0

The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

And The Survey Says…
By Brian Bailey - 25 Jun, 2020 - Comments: 0

Some of you may have received an email recently that looks something like this. Others may be getting it in a little while. This is an invitation to participate in a survey that is important for the industry, and I encourage you not to ignore it. Let me explain a little. This survey has quite a long history. It all started in 2002 when Collett International conducted the first survey. Ba... » read more

Over-Design, Under-Design Impacts Verification
By Ann Mutschler - 25 Jun, 2020 - Comments: 0

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

2020 CEO Outlook
By Ed Sperling - 25 Jun, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the semiconductor industry's outlook and what's changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the... » read more

EDA In The Cloud — Why Now?
By Mentor, a Siemens Business - 24 Jun, 2020 - Comments: 0

What is the value of cloud computing to my company? Learn how the cloud became a viable option for IC verification, and explore the ways your company can best use cloud resources to expand your compute options for both established nodes and leading-edge technologies. To read more, click here. » read more

Simplifying And Speeding Up Verification
By Ed Sperling - 16 Jun, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Using Calibre For Advanced IC Packaging Verification And Signoff
By Mentor, a Siemens Business - 10 Jun, 2020 - Comments: 0

As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

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