tag: verification

Universal Verification Methodology Running Out Of Steam
By Ann Mutschler - 30 Jul, 2020 - Comments: 2

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

Linting RISC-V Designs
By Alex Gnusin - 30 Jul, 2020 - Comments: 0

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions and their flexibility creates a problem when choosing the most reliable and robust solution from a number of contenders. Sure, a RISC-V IP design must be compliant to basic ISA standards and should contain a testing suite demonstrating that compliance. But sh... » read more

Formal Verification Of Floating-Point Hardware With Assertion-Based VIP
By OneSpin Solutions - 29 Jul, 2020 - Comments: 2

Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the ... » read more

Methodology Vs. Problem-Solving
By Hagai Arbel - 22 Jul, 2020 - Comments: 1

When I was 18, I bought a Vespa ’67: the famous Italian scooter. It was already very old then, totally beaten-up, but luckily I had a friend who owned an auto-repair shop, and he was kind enough to give me some access at night. For several weeks, I taught myself the art of metal bodywork, ending up with a beautiful metallic sky-blue ‘67 Vespa. God, I loved that machine! Then one day, ... » read more

Why Safety-Critical Verification Is So Difficult
By Ann Mutschler - 15 Jul, 2020 - Comments: 0

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Vtech: Bus Performance, FPGA Debug
By Brian Bailey - 15 Jul, 2020 - Comments: 0

It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short. If you do a search for them, you will probably find a company that sells baby monitors and kids toys. This is not that company. So, let's make sure you have the right web address to start with https://vtech-usa.com/ or https://vtech-inc... » read more

Machine Learning Enabled Root Cause Analysis For Low Power Verification
By Himanshu Bhatt - 13 Jul, 2020 - Comments: 0

By Himanshu Bhatt and Susantha Wijesekara Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. Designers and verification engineers using static verification technologies for low power often see many violations in the initial stages. Efficient debugging and determining root cause is a real issue and ... » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

Next Challenge: Known Good Systems
By Ed Sperling - 07 Jul, 2020 - Comments: 0

The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge. This doesn't mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme t... » read more

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