tag: verification

A Specification-Driven Methodology For The Design And Verification Of Reset Domain Crossing Logic
By Mentor, a Siemens Business - 25 Sep, 2019 - Comments: 0

Reset architectures have increased in complexity along with SoC designs. Sadly, traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a three-step specification-driven methodology that provides a requirements-based approach for reset domain crossing design and verification. To ... » read more

Ensuring A 5G Design Is Viable
By Ed Sperling - 09 Sep, 2019 - Comments: 0

Ron Squiers, network solutions specialist at Mentor, a Siemens Business, explains what’s different in 5G chips versus 4G, how to construct a front haul and back haul system so it is testable in the network stack. » read more

The Race For Better Computational Software
By Ed Sperling - 05 Sep, 2019 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to talk about computational software, why it's so critical at the edge and in AI systems, and where the big changes are across the semiconductor industry. What follows are excerpts of that conversation. SE: There is no consistent approach to how data will be processed at the edge, in part because there is no consis... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Enabling Faster Design, Verification and Debug of FPGAs
By Synopsys - 04 Sep, 2019 - Comments: 0

Field programmable gate arrays (FPGAs) are no longer the co-processor of full-custom chips and application-specific integrated circuits (ASICs). Today’s FPGA offerings include devices as large and complex as any ASIC system-on-chip (SoC) on the market. The dramatic increase in size, complexity and functionality means that many FPGA development teams are adopting ASIC-style design, verificatio... » read more

Clock Domain Crossing Signoff Through Static-Formal-Simulation
By Sudeep Mondal - 22 Aug, 2019 - Comments: 0

By Sudeep Mondal and Sean O'Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the majority of IP and SoC teams are focusing on “Structural CDC” analysis, which is important but not sufficient. Structural CDC analysis ensures that the d... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Improving Verification Predictability And Efficiency Using Big Data
By Mentor, a Siemens Business - 21 Aug, 2019 - Comments: 0

By providing a Big Data infrastructure, with state of the art technologies, within the verification environment, the combination of all verification metrics allows all resources to be used as efficiently as possible and enables process improvements using predictive analysis. This paper covers the technology, the metrics, and the process, and it will explore a number of techniques enabled by suc... » read more

Debug Tools Are Improving
By Brian Bailey - 12 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

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