tag: verification

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

Holistic Verification and Validation of Automotive IP for Functional Safety SoCs
By Synopsys - 03 Jul, 2024 - Comments: 0

Automotive functional safety systems have strict requirements to help avoid damages to life and property in case of a failure. As technology becomes more complex, there are increasing safety-related risks from systematic failures and random hardware failures that must be considered during product development. Standards like ISO 26262 provide guidance to mitigate such safety-related risks, by de... » read more

Verification Tools Straining To Keep Up
By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Data Coherence Across Silos And Hierarchy
By Brian Bailey - 27 Jun, 2024 - Comments: 0

Shift left has become a rallying cry for the chip design industry, but unless coherent data can flow between the groups being impacted, the value may not be as great as expected. Shift left is a term that encompasses attempts to bring analysis and decision-making forward in the development process. The earlier an issue can be found, the less of a problem it ultimately becomes. But in many ca... » read more

An LLM Approach For Large-Scale SoC Security Verification And Policy Generation (U. of Florida)
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A technical paper titled “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation” was published by researchers at the University of Florida. Abstract: "Contemporary methods for hardware security verification struggle with adaptability, scalability, and availability due to the increasing complexity of the modern system-on-chips (SoCs). ... » read more

Toward A Software-Defined Hardware World
By Karen Heyman - 06 Jun, 2024 - Comments: 0

Software-defined hardware may be the ultimate Shift Left approach as chip design grows closer to true co-design than ever with potential capacity baked into the hardware, and greater functionality delivered over the air or via a software update. This marks another advance in the quest for lower power, one that’s so revolutionary that it’s upending traditional ideas about model-based systems... » read more

Techniques To Identify Reset Metastability Due To Soft Resets
By Siemens EDA - 05 Jun, 2024 - Comments: 0

Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. These complex reset architectures with multiple reset domains, ensure functional recovery from hardware failures and unexpected electronic faults. But the transmission of data across sequential elements that are reset by different asynchronous and soft reset ... » read more

Why IC Design Safety Nets Have Limits
By Ann Mutschler and Adam Kovac - 04 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss different responsibilities in design teams and future changes in tools with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager at Siemens EDA; Dirk Seynhaeve, vice president of business development at Sigasi; Simon Davidmann, formerly... » read more

Chip Design Digs Deeper Into AI
By Ann Mutschler - 03 Jun, 2024 - Comments: 0

Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

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