Merging Verification With Validation

By Brian Bailey - 22 Mar, 2018 - Comments: 3

Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

DO-254: Increasing Verification Coverage By Test

By Aldec - 21 Mar, 2018 - Comments: 0

Verification coverage by test is essential to satisfying both the objectives of DO-254 and interpretation in FAA Oder 8110.105. However, verification of requirements by test during final board testing is challenging and time-consuming in most cases. This white paper explains the reasons behind these challenges and provides recommendations for how to overcome them. The recommendations center ... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs

By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Debugging Debug

By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Inside UVM, Take Two

By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

AI And Machine Learning Drive New SoC Verification Choices

By Frank Schirrmeister - 22 Feb, 2018 - Comments: 0

I have previously written about the choices that design teams have when choosing specific verification engines—virtual, formal, simulation, emulation, FPGA and actual silicon. As a new class of SoC is emerging for machine learning and artificial intelligence with complexities previously unheard of, they further deepen the challenge of choosing the right tool for the job. Even the choice betwe... » read more

The Value Of Trust

By John Ronco - 12 Feb, 2018 - Comments: 0

It took 40 years for Alexander Graham Bell’s telephone to go from 10% to 40% global saturation. The smartphone repeated that market penetration in less than a tenth of the time. But even the success of the smartphone is being eclipsed by the lightning pace at which Internet of Things (IoT) products are being born, with Gartner predicting that 95% of all technology products will be IoT-capable... » read more

Bridging Machine Learning’s Divide

By Brian Bailey - 08 Feb, 2018 - Comments: 0

There is a growing divide between those researching [getkc id="305" comment="machine learning"] (ML) in the cloud and those trying to perform inferencing using limited resources and power budgets. Researchers are using the most cost-effective hardware available to them, which happens to be GPUs filled with floating point arithmetic units. But this is an untenable solution for embedded infere... » read more

How Robust Is Your ESD Protection? Are You Sure?

By Derong Yan - 08 Feb, 2018 - Comments: 0

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

DVCon Committee Picks

By Brian Bailey - 25 Jan, 2018 - Comments: 0

A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting loaded with added complexity from heterogeneous multi-core systems, functional safety, neural networks and security-in addition to increasing size. Companies that do not keep up with the lates... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?