tag: verification

Follow The Moving Money
By Ed Sperling - 18 Jan, 2018 - Comments: 1

Semiconductor economics are changing by market, by region, and by product node and packaging type, adding new complexity into decisions about which technology to use for which products and why. Money is the common denominator in all of these decisions, whether it's measured by return on invested capital, quarterly profits, or long-term investments that can include acquisitions, organic growt... » read more

Getting Serious About Chiplets
By Ann Mutschler - 08 Jan, 2018 - Comments: 0

Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

Which Verification Engine?
By Ed Sperling - 02 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Reflections On 2017: Manufacturing And Markets
By Brian Bailey - 28 Dec, 2017 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

And The Winner Is…
By Brian Bailey - 21 Dec, 2017 - Comments: 0

Finding out what resonates with our readers is important, so each year I look back through the list of the best-read articles for the channels that I write for. While this simple strategy does favor articles published during the early part of the year, the fact that our readership continues to grow, partially offsets this bias. For example, in Low Power/High Performance (LPHP) a quarter of the ... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

Design Chains Will Drive The Top 5 EDA Trends In 2018
By Frank Schirrmeister - 21 Dec, 2017 - Comments: 0

In my prediction piece last year, I made seven trend predictions. Looking back, I did very well compared to what actually happened. For 2018, I am cutting it down to five trends that will impact EDA, but in my mind a lot of the trends will be driven by the ever-evolving ecosystem of design chains from IP though semiconductor to systems and to OEMs. While HBO’s 'Game of Thrones' comes to a con... » read more

Mixing Interface Protocols
By Ann Mutschler - 21 Dec, 2017 - Comments: 0

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems
By Ron Squiers - 14 Dec, 2017 - Comments: 0

As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

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