tag: verification

Tech Talk: Substrate Noise Coupling
By Ed Sperling - 14 Dec, 2017 - Comments: 0

Roland Jancke, head of the department for design methodology for the Fraunhofer's Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about the impact of substrate noise coupling on reliability of chips and how to deal with this issue. https://youtu.be/7E2rCwYr6-o » read more

Co-modeling: A Powerful Capability For Hardware Emulation
By Mentor, a Siemens Business - 13 Dec, 2017 - Comments: 0

Understanding co-modeling technology, its impact on verification and validation should be a critical aim for anyone selecting and deploying emulation co-modeling resources. This paper explores how emulation co-modeling — specifically for the Veloce Strato emulation platform from Mentor, a Siemens business — is architected to meet the needs of advanced verification and validation. To rea... » read more

Advanced Packaging Is Suddenly Very Cool
By Ed Sperling - 11 Dec, 2017 - Comments: 2

The hottest chip markets today—automotive AI for autonomous and heavily assisted driving, machine learning, virtual and augmented reality—all are beginning to look at advanced packaging as the best path forward for improving performance and reducing power. Over the past four years, which is when 2.5D and fan-out wafer-level packaging first really began garnering interest, these and othe... » read more

UVM Can Kill You. More News At 11
By Neil Johnson - 04 Dec, 2017 - Comments: 0

Ok. I agree. Not a great title. I don’t like it either. Some pretty aggressive clickbait, I know. But it’s got the quick hit, newsy cliffhanger feel that makes you want to tune in anyway, doesn’t it? I had to go for it. For what it’s worth, it wasn’t my first choice. I wanted to go with “What You Don’t Know About UVM Can Kill You. More News at 11”. Same punch. Still the hi... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

Using FPGAs For Emulation
By Krzysztof Szczur - 30 Nov, 2017 - Comments: 0

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Tech Talk: Verification
By Ed Sperling - 30 Nov, 2017 - Comments: 0

Frank Schirrmeister, Cadence's senior group director for verification platforms, talks about what's changing in verification with 5G, machine learning, greater connectivity, advanced packaging, and the growing need to build security into designs. https://youtu.be/GMF8BkmdJzE » read more

High-Performance 7nm IP Verification With The AFS Platform At Silicon Creations
By Mentor, a Siemens Business - 29 Nov, 2017 - Comments: 0

While there are many benefits to migrating to smaller process geometries, such as lower power and higher performance, the increased design complexity places an even higher burden on fast and efficient simulation technology. In addition, fast and accurate resistor/capacitor (RC) extraction is becoming increasingly important. Interconnect resistance is an increasing percentage of the total path r... » read more

An Incremental Approach To Reusing Automated Tests From IPs To SoCs
By Matthew Ballance - 09 Nov, 2017 - Comments: 0

Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

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