tag: verification

Worst-Case Results Causing Problems
By Ed Sperling - 09 Mar, 2017 - Comments: 0

The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to create its own set of issues. This is particularly true at 16/14nm and below, where extra circuitry can slow performance, boost the amount of power required to drive signals over longer, thinne... » read more

Synopsys SoundWire Test Suite
By Synopsys - 08 Mar, 2017 - Comments: 0

Validation and interoperability are always a challenge for any new protocol. An earlier white paper, Digital Audio Simplified: MIPI SoundWire, discussed the basics of digital audio transmission, and benefits of SoundWire over other audio interfaces. This whitepaper describes how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite. To read more, cli... » read more

Quality Issues Widen
By Ed Sperling - 06 Mar, 2017 - Comments: 0

As the amount of semiconductor content in cars, medical and industrial applications increases, so does the concern about how long these devices will function properly—and what exactly that means. Quality is frequently a fuzzy concept. In mobile phones, problems have ranged from bad antenna placement, which resulted in batteries draining too quickly, to features that take too long to load. ... » read more

Why Auto Designs Take So Long
By Ann Mutschler - 02 Mar, 2017 - Comments: 0

Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements. On the verification side it could result in an additional 6 to 12 months of work. On the design side, developing the same processor in the mobile market would take 6 fewer man months. And when it comes to complex electronic control units (ECUs) or [getkc id="81... » read more

Could DVCon Be Better?
By Brian Bailey - 23 Feb, 2017 - Comments: 0

DVCon is undoubtedly the best conference in the industry if your interest is functional verification. In the past, it has also had a slant toward design. The focus is quite simply based on the standards activity going on within [getentity id="22028" e_name="Accellera"], the EDA industry's body that turns problems into solution in a short space of time. As those standards mature, they are handed... » read more

Better Code With RTL Linting And CDC Verification
By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017
By Frank Schirrmeister - 23 Feb, 2017 - Comments: 0

DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!
By Dave Kelf - 23 Feb, 2017 - Comments: 0

If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

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