tag: verification

The Early Bird Catches The Bug Using Formal
By Dave Kelf - 28 Apr, 2016 - Comments: 0

It has been suggested that formal might replace simulation, at least in some parts of the design flow. Not likely! The question is, how can formal be layered on top of simulation flows to improve coverage and schedule? The way formal is being used at the larger semiconductor companies is evolving. In many of these companies a small team of hardcore formal experts are employed across differen... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

UVM Register Layer: The Structure
By Henry Chan - 28 Apr, 2016 - Comments: 0

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors who can then poke, prod, and examine us remotely. This is essentially what the UVM register layer allows and does. The UVM register layer acts similarly by mod... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 Apr, 2016 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifie... » read more

SoC Verification Made Easy
By Aldec - 27 Apr, 2016 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, there-fore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This docu... » read more

Formal Verification Applied To The Renesas MCU Design Platform Using OneSpin Tools
By OneSpin Solutions - 27 Apr, 2016 - Comments: 0

An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 26 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

RTL Done And Other Bogus Development Milestones
By Neil Johnson - 28 Mar, 2016 - Comments: 0

My definition of progress has changed over the years. I don’t think about it much anymore but it was obvious in a talk I gave a few weeks ago to a diverse group of hardware developers. Part of that talk centered around how we define progress in design and verification. This is a normal thing for me; I was speaking to slides I’d used several times before and the message was no different than... » read more

It’s Transition Time
By Ed Sperling - 24 Mar, 2016 - Comments: 1

For the past couple of years we've been hearing about the coming onslaught of the IoT, difficulties in scaling device features and a shift left that will redefine verification, debug and software prototyping. It's all happening. Taken individually, these are noteworthy changes. Taken as a whole, they represent a massive repositioning of the semiconductor industry, from architectural explorat... » read more

A Formal Transformation
By Brian Bailey - 24 Mar, 2016 - Comments: 0

A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

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