tag: verification

Applying Lessons Of Mass Production To Verification
By Larry Vivolo - 12 Feb, 2015 - Comments: 0

I’ve recently been experiencing that time-honored tradition of helping an elderly family member as they go through one surgery after another attempting to restore worn-out, miscellaneous body parts. What’s most surprising, beyond the costs, is that shopping for a knee or disc replacement is much like shopping for a car. Do you go for the high-performance knee, which maybe hasn’t been test... » read more

Accellera Adds Portable Stimulus Group
By Brian Bailey - 11 Feb, 2015 - Comments: 0

[getentity id="22028" e_name="Accellera"] created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow. This is a big deal in verification because it allows horizontal reuse of a [getkc id="55" kc_name="testbench"]. Test patterns run on the processors in a design and that enables the test to ... » read more

Blog Review: Feb. 11
By Jesse Allen - 11 Feb, 2015 - Comments: 0

Ansys' Bill Vandermark flags the top five engineering articles of the week. Check out the one about the latest attempt at cold fusion, which left researchers hiding behind a blast shield. The solar-powered car named Stella drove away with the prestigious "Best Technology Achievement" award at the 8th annual Crunchies Awards this week. NXP's Maurice Geraets sounds like a proud parent – with... » read more

Software-Driven Verification (Part 3)
By Brian Bailey - 10 Feb, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

What Will 2015 Bring For System-On-Chip Verification?
By Frank Schirrmeister - 29 Jan, 2015 - Comments: 0

Starting a new year, I always look back at predictions from years past to see how far off they were from reality and try to understand why. Rolling back 10 years, IEEE Spectrum published its annual “Winners and Losers” issue. Looking back, three predictions stick out for me. The first one is about how we consume media. Back in the January 2005 issue of IEEE Spectrum, Internet Protocol T... » read more

Speeding Up Timing Constraint Creation, Refinement And Validation
By Divya Macharla - 29 Jan, 2015 - Comments: 0

We are dealing with designs integrating many features and working with cutting-edge process technologies. Design methodologies and the design and process complexities can be overwhelming. To leverage the advancements in EDA tools and to achieve optimal power, performance and area results while overcoming design complexities, it is important to have a qualitative timing constraint file that c... » read more

Blog Review: Jan. 28
By Ed Sperling - 28 Jan, 2015 - Comments: 0

Mentor Graphics' John Day points to the growing presence of automakers in Silicon Valley. The latest émigré is Ford, which is setting up a research and innovation center in Palo Alto, but the company is hardly alone. Electronics could well become the real differentiators in vehicles. ARM's Andrew Sloss points to an intriguing relationship between data and economic growth—not to mention m... » read more

Unraveling Power Methodologies
By Brian Bailey - 15 Jan, 2015 - Comments: 0

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

IP Design Essentials For Reliability And SoC Integration
By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

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