tag: verification

A History of (Premature) Optimization
By Neil Johnson - 22 Dec, 2015 - Comments: 0

I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left writing and been advocating for agile development, this kind of comparison is more than a little odd to see. It’s a comparison between two as yet amorphous development strategies, neither of which i... » read more

The Beginning
By Anupam Bakshi - 22 Dec, 2015 - Comments: 0

We all want our creations to transcend time. Our products, our designs—even our specifications. Specifications are more than just ideas or collections of requirements or static collections of implementation details. They live inside many chips and many designs, and the more flexible and portable they are, the longer they remain relevant. End devices may be replaced relatively quickly, but ... » read more

Outlook 2016 – The year of Horizontal and Vertical Flow Integration
By Frank Schirrmeister - 22 Dec, 2015 - Comments: 0

As 2015 comes to an end rapidly, the key question becomes what the next year will bring. Last year around this time, in my blog “The Next Big Shift In Verification”, I talked about software-driven verification as the next era of verification that follows the eras of directed testing and High-level Verification Language (HVL) driven verification. I also had referred to our System Development... » read more

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

Reflections On 2015
By Brian Bailey - 22 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

Who’s Profiting From Complexity
By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

Safety in SoCs
By Synopsys - 09 Dec, 2015 - Comments: 0

Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deploy... » read more

Low Power Design Analysis
By Ansys - 09 Dec, 2015 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To read more, click here. » read more

Defining Sufficient Coverage
By Brian Bailey - 07 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

Addressing The Challenges Of IoT Design
By Mentor, a Siemens Business - 03 Dec, 2015 - Comments: 0

Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. The Tanner design flow is architected to seamlessly work in any of these design domains by employing an integrated design flow for desi... » read more

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