tag: virtual platforms

Toward Software-Defined Vehicles
By Ed Sperling - 24 Jul, 2024 - Comments: 0

Speed is everything when it comes to designing automotive electronics, but not in the usual way. In the past, product cycles often lasted five to seven years, from initial design to implementation inside of vehicles. That no longer works as vehicles adopt more electronic features to replace mechanical ones, and as competition heats up over the latest features and nearly instantaneous over-the-a... » read more

OVP Guide To Using Processor Models
By Imperas - 24 Feb, 2021 - Comments: 0

The OVP simulation technology from Open Virtual Platforms (OVP) and Imperas Software Limited enables very high performance simulation, debug and analysis of virtual platforms containing multiple processor and peripheral models. The OVP technology is extensible, provides the ability to create new models of processors and other platform components by writing C/C++ code that uses application progr... » read more

Verification Throughput Is Set To Increase By Leaps And Bounds In 2019
By Frank Schirrmeister - 20 Dec, 2018 - Comments: 0

In June 2015, I wrote the blog “Towards A Metric To Measure Verification Computing Efficiency” that introduced what we now refer to here at Cadence as the “productivity wheel” for verification payloads—the sequence of “build”, “allocate”, “run” and “debug” that is repeated thousands of times during a project. It was meant to set up the launch of the Palladium Z1 platfo... » read more

Virtual Design Chains At The EDA Forum
By Frank Schirrmeister - 29 Nov, 2018 - Comments: 0

The German edacentrum’s EDA Forum was held in Berlin, Germany, in early November. It was very interesting to see the design chain effects in the automotive domain, very visible in a panel yours truly was part of, together with Audi, Bosch, Infineon, MicroChip, Synopsys, Mentor, and the BMBF. Driven from the top of the design chain, the direction is clearly to go more virtual to optimize the c... » read more

DAC 2018: System Design, Cloud And Machine Learning
By Frank Schirrmeister - 28 Jun, 2018 - Comments: 0

This marks the 10th DAC that I have covered as a blogger. At DAC 2008 in Anaheim, the industry had just come together behind the SystemC TLM 2.0 standard to enable virtual platforms, finally getting to model interoperability. System design is the common thread that is also present in this year’s DAC in 2018 in San Francisco. But a lot has changed. Big data analytics, artificial intelligence a... » read more

Hidden Costs Of Shifting Left
By Brian Bailey - 26 Apr, 2018 - Comments: 0

The term "Shift Left" has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks. One such example being talked about today is the need to perform hardware/software integration much earlier in the flow, rather than leaving it as a sequ... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Aldec HES Emulation Integration With Imperas OVP
By Aldec - 29 Jun, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

What Is Functional Accuracy?
By Ann Mutschler - 26 Mar, 2015 - Comments: 0

What it means to be functionally accurate in the context of [getkc id="104" kc_name="virtual platforms"] varies greatly, depending upon whom you ask and even when you ask them. But that doesn’t mean that functional accuracy isn’t useful. Jon McDonald, technical marketing engineer for the design and creation business at [getentity id="22017" e_name="Mentor Graphics"], expects to see a lot... » read more

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