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Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process


Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Eliminating Ground-Loop Induced Noise


As semiconductor device performance increases, especially for low power and higher speed ICs, testing low frequency 1/f, RTN and phase noise with improved signal-to-noise ratio is required. Finding and eliminating unwanted noise is required in multiple areas. Noise sources can be found inside a prober, outside a prober, and in a measurement TestCell. Historically, TestCell-generated noise was o... » read more

What’s WAT? An Overview Of WAT/PCM Data


Wafer acceptance testing (WAT) also known as process control monitoring (PCM) data is data generated by the fab at the end of manufacturing and generally made available to the fabless customer for every wafer. The data will typically have between forty and one hundred tests, each test having a result for each site (or “drop-in”) on the wafer. The sites are located so that the fab can monito... » read more

New Test Methods For 5G Wafer High-Volume Production


In order to provide the chips required for this change in the landscape, there will be a large number of changing requirements in wafer test that come out of these architectural requirements. Form Factor partnered with Intel to investigate these changes, and tested one such example of a new test methodology. In a joint collaboration with Intel to develop a test methodology for their 5G RF-So... » read more

Considerations For 5G Production Test


Like all technology advancements, bringing 5G to market requires an array of supporting tools to ensure the end products meet expectations. It will require significant performance advances in chip technology and manufacturing processes—all the while keeping price/performance at an economically viable level. Earlier this year, FormFactor’s Daniel Bock along with Jeff Damm outlined three c... » read more

Probing From Home


The current stay-at-home, work-from-home situation challenges the semiconductor industry in a way we have never seen before. Social distancing and remote work put operational procedures in place that can be difficult. In a previous post, we shared information on our virtual demos designed to help keep your semiconductor measurements running no matter where you are physically located. In this ... » read more

Test Setup Optimization And Automation For Accurate Silicon Photonics Wafer Acceptance Production Tests


Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and... » read more

Heating Up Cryogenic Wafer Testing


The use of on-wafer superconducting materials, other novel materials, and traditional semiconductors at cryogenic temperatures (below about 123K, or -150°C) has grown quickly in recent years. Inventive new sensors take advantage of unique material properties at very low temperatures to detect a wide variety of physical phenomena such as infrared radiation, magnetic fields, x-rays, and more. T... » read more

What’s WAT? Testing At The End Of Manufacturing


The high costs of building, resourcing and operating a foundry fabricating integrated circuits are well known. Fabless companies avoid this capital cost and focus on design and innovation in their area of expertise. On the other hand, the fabless company relies on the expertise and skills of the foundry to produce quality wafers. Many times a process used by a fabless company to manufacture... » read more

Wafer Test Challenges For Chiplets


In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage. From a test perspective, making chiplets a mainstream technology depends on ensuring Good Enough Die at a reasonable test cost. Wafer-level test plays a critical and intricate role in the chipl... » read more