tag: wafer test

The Test Cell Ecosystem: From Tester Performance To Production Outcomes
By Denis Kang - 07 Jul, 2026 - Comments: 0

In semiconductor manufacturing, tester performance has traditionally been the focal point of evaluation, encompassing speed, accuracy, and measurement capability. Yet even the most advanced tester depends on something broader to fully realize optimal throughput, yield, and overall equipment efficiency (OEE) in a production environment: the test cell. This distinction is becoming more pronoun... » read more

From Reactive Replacement To Predictive Planning: Unlocking Probe Card Intelligence With Real-Time Data
By Arik Peltz - 07 Jul, 2026 - Comments: 0

Probe cards are among the most critical — and costly — assets in wafer test. Even if production line typically prepares on-demand spares, unexpected failure can cause significant downtime and production loss. One of the most persistent challenges is tip-burn degradation: gradual probe tips wear that ultimately leads to failure. A new technical initiative explores whether DC profiling dat... » read more

Need For KGD Drives Singulated Die Screening
By Anne Meixner - 31 Mar, 2025 - Comments: 2

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly higher than with a single die. Better methods for inspecting and testing these devices are already starting to roll out. High-throughput infrared inspection is capable of catching more sub-surface d... » read more

Deploying Cutting-Edge Adaptive Test Analytics Apps
By Ken Butler - 12 Dec, 2023 - Comments: 0

By Ken Butler, Advantest, and Guy Cortez, Synopsys Semiconductor test challenges abound in this era of AI. As such, semiconductor test engineering is increasingly moving towards fully adaptive test where each device receives the “right” test content to assess its correctness. Advantest and Synopsys have partnered to provide new cutting-edge real-time adaptive test applications at the te... » read more

Enablers And Barriers For Connecting Diverse Data
By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Coping With Parallel Test Site-to-Site Variation
By Anne Meixner - 09 Nov, 2021 - Comments: 1

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each device under test (DUT) is a multi-physics problem, and it's one that is becoming more essential to resolve at each new process node and in multi-chip packages. It requires synchronization of el... » read more

Production Testing For Silicon Photonics Wafers
By David Viera - 10 Aug, 2021 - Comments: 0

Worldwide data centers and networks for communications currently consume about 8% of the Earth’s total energy produced. To meet the increasing demands for cloud storage, computing, and various emerging applications such as artificial intelligence, genomics revolution, and video transcoding, hyperscale data centers are being built around the world at an accelerated pace, with analysts predicti... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Eliminating Ground-Loop Induced Noise
By Peter Andrews - 13 Oct, 2020 - Comments: 0

As semiconductor device performance increases, especially for low power and higher speed ICs, testing low frequency 1/f, RTN and phase noise with improved signal-to-noise ratio is required. Finding and eliminating unwanted noise is required in multiple areas. Noise sources can be found inside a prober, outside a prober, and in a measurement TestCell. Historically, TestCell-generated noise was o... » read more

What’s WAT? An Overview Of WAT/PCM Data
By yieldHUB - 12 Oct, 2020 - Comments: 0

Wafer acceptance testing (WAT) also known as process control monitoring (PCM) data is data generated by the fab at the end of manufacturing and generally made available to the fabless customer for every wafer. The data will typically have between forty and one hundred tests, each test having a result for each site (or “drop-in”) on the wafer. The sites are located so that the fab can monito... » read more

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