tag: X-ray inspection

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

SiC Growth For EVs Is Stressing Manufacturing
By Anne Meixner - 08 Aug, 2023 - Comments: 0

The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips. Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and t... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 16 Jun, 2023 - Comments: 0

Applied Materials sued its Chinese-owned rival, Mattson, over an alleged 14-month effort to steal valuable trade secrets, reports Bloomberg. In court filing, Applied Materials claimed that Mattson engaged in a spree of employee-poaching and covertly transferring semiconductor equipment designs. Global semiconductor materials revenue grew 8.9% to $72.7 billion in 2022, surpassing the previous... » read more

3D Structures Challenge Wire Bond Inspection
By Karen Heyman - 09 May, 2023 - Comments: 1

Adding more layers in packages is making it difficult, and sometimes impossible, to inspect wire bonds that are deep within the different layers. Wire bonds may seem like old technology, but it remains the bonding approach of choice for a broad swath of applications. This is particularly evident in automotive, industrial, and many consumer applications, where the majority of chips are not de... » read more

Metrology Strategies For 2nm Processes
By Laura Peters - 07 Mar, 2023 - Comments: 3

Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the bo... » read more

Standards: The Next Step For Silicon Photonics
By Karen Heyman - 07 Mar, 2023 - Comments: 0

Testing silicon photonics is becoming more critical and more complicated as the technology is used in new applications ranging from medicine to cryptography, lidar, and quantum computing, but how to do that in a way that is both consistent and predictable is still unresolved. For the past three decades, photonics largely has been an enabler for high-speed communications, a lucrative market t... » read more

Bump Reliability is Challenged By Latent Defects
By Karen Heyman - 07 Feb, 2023 - Comments: 0

Thermal stress is a well-known problem in advanced packaging, along with the challenges of mechanical stress. Both are exacerbated by heterogenous integration, which often requires mingling materials with incompatible coefficients of thermal expansion (CTE). Effects are already showing up and will likely only get worse as package densities increase beyond 1,000 bumps per chip. “You comb... » read more

Legacy Tools, New Tricks: Optical 3D Inspection
By Karen Heyman - 08 Nov, 2022 - Comments: 0

Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
By Karen Heyman - 11 Oct, 2022 - Comments: 0

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Fundamental Shifts In IC Manufacturing Processes
By Ed Sperling - 14 Mar, 2022 - Comments: 2

High chip value and 3D packaging are changing where and how tests are performed, tightening design-for-reliability and accelerating the shift of tools from lab to fab. Heterogeneous integration and more domain-specific designs are causing a string of disruptions for chip manufacturers, up-ending proven fab processes and methodologies, extending the time it takes to manufacture a chip, and ul... » read more

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