Startup Funding: July 2021


The trend of big funding for Chinese autonomous driving companies continued in July, with three startups each drawing $100M or more for efforts in ADAS and computer vision for automotive. The month also saw one electric vehicle manufacturer get a massive boost as it begins production on its first models, while significant funding also went to a company that wants to recycle used up EV batteries... » read more

Week In Review: Design, Low Power


Tools Vtool released a new version of its Cogita visual debug platform. New features aim to provide faster debug capabilities, including visual representation of test results using log files as input, improved manipulation and navigation throughout big logs, ML algorithms to classify data and find the relationship between inputs, and the ability to merge and compare test flow of two different ... » read more

Challenges For New AI Processor Architectures


Investment money is flooding into the development of new AI processors for the data center, but the problems here are unique, the results are unpredictable, and the competition has deep pockets and very sticky products. The biggest issue may be insufficient data about the end market. When designing a new AI processor, every design team has to answer one fundamental question — how much flex... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO


Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Xilinx is investing an undisclosed amount in fabless semiconductor startup Kameleon Security, which is working on a cyber protection chip for servers, data centers, and cloud computing. The proactive Security Processing Unit (ProSPU) already secures the boot and has a root of trust (RoT). The chip will be demonstrated at the Open Compute Project (OCP) Global Summit, which is planned f... » read more

Week In Review: Design, Low Power


Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Week In Review: Auto, Security, Pervasive Computing


Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Safe And Robust Machine Learning


Deploying machine learning in the real world is a lot different than developing and testing it in a lab. Quenton Hall, AI systems architect at Xilinx, examines security implications on both the inferencing and training side, the potential for disruptions to accuracy, and how accessible these models and algorithms will be when they are used at the edge and in the cloud. This involves everything ... » read more

Accelerating 5G Baseband With Adaptive SoCs


5G new radio (NR) network specifications demand new architectures for radio and access networks. While the 5G NR architecture includes new spectrum and massive MIMO (mMIMO) antennas, corresponding access networks architecture must also evolve to implement the services defined by 5G, which include enhanced Mobile Broadband, Ultra Reliable Low Latency Communications and massive Machine Type Commu... » read more

Reducing Power Delivery Overhead


The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

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