tag: Xilinx

Week In Review: Design, Low Power
By Jesse Allen - 23 Aug, 2019 - Comments: 0

Xilinx debuted the Virtex UltraScale+ VU19P, which the company says is now the world's largest FPGA at 1.6X the size of its predecessor. The VU19P features 35 billion transistors, 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. With a set of debug, visibility tools, and IP,... » read more

Advanced Packaging Options Increase
By Ed Sperling - 19 Aug, 2019 - Comments: 0

Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high performance is one of the main criteria. At least part of the problem is there is a spectrum of choices, which makes it hard to achieve economies of scale. Even where there is momentum for a particular ... » read more

Debate Over Health Of Moore’s Law Continues
By Ann Mutschler - 10 Jul, 2019 - Comments: 0

Semicon West 2019 was kicked off by the ‘AI Design Forum’ and featured a panel of CEOs that debated if Moore’s Law was still making power, performance and area optimization possible in the same way as it had been. Synopsys chairman and co-CEO Aart de Geus asserted that Moore’s Law is completely alive. “The discussion of Moore's Laws invariably goes back to the ‘65 document, and t... » read more

Falling Chip Forecasts
By Mark LaPedus - 20 Jun, 2019 - Comments: 1

It’s time to take a pulse of the semiconductor market amid the memory downturn and trade frictions with China. For some time, the DRAM and NAND markets have been hit hard with falling prices and oversupply. Then, the Trump administration last year slapped tariffs on Chinese goods. China retaliated. And the trade war rages on between the U.S. and China. More recently, the U.S. Department... » read more

Data Confusion At The Edge
By Ed Sperling - 11 Jun, 2019 - Comments: 0

Disparities in pre-processing of data at the edge, coupled with a total lack of standardization, are raising questions about how that data will be prioritized and managed in AI and machine learning systems. Initially, the idea was that 5G would connect edge data to the cloud, where massive server farms would infer patterns from that data and send it back to the edge devices. But there is far... » read more

Machine Learning Drives High-Level Synthesis Boom
By Kevin Fogarty - 06 Jun, 2019 - Comments: 0

High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts. The obvious advantage of HLS is the boost in productivity designers get from working in C, C++ and other high-level languages rather than RTL. The ability to design a layout that should work, and then easily modify it to test other confi... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 24 May, 2019 - Comments: 0

Packaging and test In the rankings, ASE was the top OSAT in terms of sales in the first quarter of 2019, according to TrendForce. Amkor and JCET were next in the rankings. “Judging from the falling phone sales 1Q19 impacted by the U.S.-China trade dispute and the oversupply situation in memory markets, the total revenue of the top ten businesses in packaging and testing are predicted to st... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Apr, 2019 - Comments: 0

Fab tools and test Lam Research has developed a new self-maintaining or self-cleaning chamber for its etch tools. With the technology, Lam announced a new industry benchmark has been set for productivity in etch processing using its self-maintaining equipment. Etch process modules are typically cleaned weekly or monthly. Recently, Lam and a chipmaker reached the milestone of going 365 days... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Apr, 2019 - Comments: 0

A new working group has been proposed by Accellera to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. “Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” said Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy