Ensure Zero Functional CDC Signoff Defects With VC SpyGlass Integrated Solution

By Synopsys - 06 Mar, 2024 - Comments: 0

This whitepaper will explain how designers can ensure zero defects seamlessly using Synopsys VC SpyGlass as a single cockpit for not just structural CDC analysis but also for complete functional analysis. We will also cover how designers can utilize a single dashboard for tracking the functional CDC signoff progress over the course of the project. Click here to read more. » read more

Using Deep Data Analytics To Enhance Reliability Testing The Fast Roadmap for Zero Defects

By proteanTecs - 10 Oct, 2023 - Comments: 0

proteanTecs and ELES have partnered together to enhance reliability testing with deep data analytics. This collaboration enables SoC manufacturers to improve their qualification envelope to achieve lifetime reliability, shorten their root cause analysis time, and reduce operational costs. This innovative approach adds parametric measurements during the stress test in order to accurately and pre... » read more

Automotive IC Production Wafer Test In A Zero-Defect World

By FormFactor - 08 Feb, 2021 - Comments: 0

By Amy Leong, FormFactor. Innovations in automotive semiconductor ICs post a high bar for wafer test. FormFactor’s Chief Marketing Officer, Amy Leong, provides insights into the challenges associated with automotive IC production wafer testing amid the requirement for zero-defects. Click here to continue reading. » read more

Next-Generation Vehicles Pose Automotive Semiconductor Test Challenges

By Advantest - 07 May, 2019 - Comments: 0

Various market trends are driving requirements for automotive semiconductor test as technology increasingly defines the future of the automobile. According to IHS Markit, the total market for semiconductors, having reached nearly $500 billion in 2018, will grow at a CAGR of 4.88% through 2022, while the automotive electronics category, reaching more than $40 billion in 2018, will outpace the to... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: zero defects

Ensure Zero Functional CDC Signoff Defects With VC SpyGlass Integrated Solution

Using Deep Data Analytics To Enhance Reliability Testing The Fast Roadmap for Zero Defects

Automotive IC Production Wafer Test In A Zero-Defect World

Next-Generation Vehicles Pose Automotive Semiconductor Test Challenges