Ten Reasons 3D-IC Will Profoundly Change The Way You Design Electronics

3D design will force IC design teams to face new physics domains and challenges.


The history of electronic design has been defined by repeated waves of major technological change and accompanying business realignment. Many companies have foundered and disappeared when they were unable to anticipate and adjust to these powerful forces of change. Consequently, I am not alone in believing that now is the time to get ready for the next significant change to your electronic design flow, and even the way your company organizes and partitions design teams. I am convinced that designing a 2.5D or 3D multi-die stack will soon be coming to a project near you, and it will bring you face to face with physics domains and challenges that are new to many IC design teams. This conviction is based on real market data from key EDA solutions providers like Ansys who report that their multiphysics analysis tools were used on more 2.5/3D-IC design starts in 2020 alone than in the past 10 years combined.

Every time design technology changed it was done as a reaction to break through a wall, or bottleneck, that limited our progress towards ever bigger and more integrated systems. Looking back at how the semiconductor industry has accommodated these earlier paradigm shifts can teach us to better understand and adjust to this new inflection point around 3D design.

Fig. 1: History of technology bottlenecks in semiconductor design capability and how the industry has responded and changed in order to break through each time.

By the late 1980s, hand drawing of schematics and manual RTL creation were the limiting factors on taking advantage of Moore’s Law. The industry responded by adopting automation on an unparalleled scale and depth. EDA came of age with leaps in automation including logic synthesis, static timing analysis, and the automated place-and-route gate array ASIC design flow.

In the 1990s, the new bottleneck was designer productivity, and the industry reacted by developing extensive methodologies for design reuse. The intellectual property (IP) sector was born, and IP reuse became supported by all EDA tools and is now a standard component of every SoC. The business side was also realigned to reflect this change, with industry giants like Synopsys and Arm providing critical IP infrastructure to all IC designs.

The 2000s saw a technical plateau for the clock speeds that could be achieved for digital designs  at <5GHz, and this was blocking the upward trend in compute power. The industry reacted by embracing parallelism and multi-core execution. EDA tools adjusted, not least by upgrading their algorithms to make use of the very parallelism that they were being used to design in microprocessors.

The most recent shift in the 2010s came from the rise of power management to a first-order concern, not just for battery-powered applications but for everyone, including even HPC datacenters. This is what drove the technology shift to finFETs, fully depleted SOI, and ultra-low operating voltages. Electronic design practice has similarly shifted to increased emphasis on low-power design and power integrity signoff as a key technology.

Which brings us to the present day where new silicon applications like GPUs, TPUs, and AI/ML chips are overflowing maximum reticle sizes and require huge amounts of closely integrated memory. The only way these high-end systems can achieve their power and performance goals is through the intimate integration of multiple dice on an interposer substrate (2.5D-IC) or by stacking dice directly on top of each other (3D-IC and HBM). And it’s not only the high end that is adopting 3D design. There are also strong economic reasons driving the disintegration of SoCs into a heterogeneous collection of smaller die that need to be integrated on a die-to-die substrate. This move to embrace “chiplet” design is still nascent, and not yet as mature as the more traditional 2.5D and 3D design, but is currently undergoing a lot of development efforts. The technology challenges faced by 3D-IC designers are significantly altering many of our assumptions about how to go about designing chips.

Here is a list of what I believe to be the top 10 major issues to consider when considering 2.5/3D-IC design:

  1. The organizational wall between package and chip designers will need to come down. Expertise will need to be blended.
  2. Power dissipation and thermal analysis will be the limiting factors on achievable system density. They become primary design parameters.
  3. Electromagnetic coupling and non-local interference become primary concerns when running high-speed signals on 3D substrates across long distances. This has been less of an issue for short on-chip interconnects and many chip designers are unfamiliar with inductive coupling.
  4. Routing high supply currents through ever smaller microbumps and through-silicon vias (TSVs) is a significant challenge requiring novel approaches and very careful supply network analysis. This is the logical extension of structures like via pillars that are already appearing inside chips.
  5. Thermo-mechanical stress and warpage need to be part of floorplanning decisions and reliability signoff, particularly during the prototyping stage.
  6. Heterogeneous models for the many different elements that make up a multi-die system (HBM, analog die, interposer routing, digital die, redistribution layers (RDL), and more) need to be gathered and represented together for any system-level analysis. This range of data representations exceeds what most tools are capable of today.
  7. Deeper reliance on silicon foundries to provide 3D packaging technology will also come with a more formalized set of sign-off requirements, which will mark a significant change for packaging and board designers.
  8. Even small analog chips will need to be designed and qualified for integration into 3D systems. Ideally this implies low-power, short-run IO protocols, rather than the traditional IO drivers for stand-alone PCB mounting.
  9. Capacity: Sheer system design size will stress the capacity of many design and analysis tools and will require an investment in new categories of reduced order models (ROMs).
  10. The close coupling and strong interdependence of all these effects will require a multiphysics integration that goes well beyond the discrete solutions for each kind of physics that are often used today. See this Chip Package System design environment for an example of IoT multiphysics analysis.

Each of these points deserves a whole discussion in its own right, but 3D-IC is here today, and it will affect almost every step in the EDA and system design flow. I believe the companies that invest early and most rapidly adjust to this new electronic design paradigm will be the ones to reap the greatest benefits and outpace their competitors in the years ahead.


Miek Gaynor says:

I have looked at this off and on for 15 years. I agree with your points, but one thing to add is RF. This opens another can of worms. RF has gone to flip chip in many cases. It requires low ground inductance and fro PAs good thermal. I am a Rf engineer for 35 years. I worked on PCBs then RF System in packages at Amkor, and now RF IC design. I have been on both sides and agree fully that the walls need to come down between IC and package design. I saw many times where the IC was designed as small as possible to reduce cost only to drive up the package cost. The best designs were when I worked early in the design phase with the IC designers doing the package design concurrently. I did RF blocks embedded into the package.

Ronak Shah says:

Interesting read Marc!!

Marc Swinnen says:

Yes, RF design is another strong motivator in the move to 3D design. The promise is held out that it will facilitate heterogeneous assemblies where the RF section can use an optimized technology over the logic process. This is pointing down the path to chiplets, but the industry is not quite there yet to make that a reality.

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