The Challenges Of Process Control On FinFETs And FD-SOI

While both technologies face similar challenges, fundamental differences in architecture and materials require specific strategies.

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Across the semiconductor industry, both FD-SOI and finFET transistor technologies are in high volume production, with IC manufacturers looking to extend both technologies to gain additional performance improvements and meet the variety of customer specific technical and economic requirements. In developing the processes needed for the next-generation FD-SOI and finFET technologies, both transistor types face similar challenges, including the proliferation of design and process systematic defects, the erosion of process margins and increased process variability. Comprehensive process control solutions that incorporate inspection, metrology and data analytics serve a key role in helping IC manufacturers address these challenges. However, since FD-SOI and finFET transistors have fundamental differences in device architecture and materials, each requires the adoption of specific process control strategies that can help fabs detect, quantify and address process-related issues.

FD-SOI (fully depleted silicon on insulator) technology is gaining adoption in devices that serve the IoT, automotive and machine learning markets. It is currently in full production at the 28nm design node, in development for the 22nm and 12nm design nodes, and is scalable to at least 10nm. FD-SOI technology is a planar process that leverages and extends the performance of existing bulk CMOS planar manufacturing methods by using a different starting substrate. The FD-SOI substrate has an ultra-thin layer of insulator, called the buried oxide, positioned on top of the base silicon. The transistor channel consists of a very thin silicon film. By design, FD-SOI technology enables better transistor electrostatic characteristics versus conventional bulk CMOS and reduces device leakage. SOI substrates are produced by wafer manufacturers, who must implement specific inspection and metrology controls to ensure that the substrates are meeting the necessary specifications of the IC manufacturer. The wafer manufacturers rely on process control systems, including:

  • Unpatterned wafer defect inspectors to help wafer manufacturers optimize their processes and ensure that their final products are free of particles, stacking faults, slip lines, scratches, and other defects
  • Bare wafer geometry metrology systems to ensure the substrates meet flatness, edge roll off, and front and backside nanotopography requirements
  • Films metrology systems to optimize and control thickness and uniformity of the SOI film stack

The device manufacturing processes for FD-SOI are very similar to bulk silicon CMOS processing. As such, the best known methods for process control for bulk CMOS are generally applicable for FD-SOI – including use of patterned and unpatterned wafer defect inspectors for inline defect monitoring and process tool qualification. One key exception is FEOL metrology, including films metrology and overlay metrology. The thin surface stack for FD-SOI substrate is transparent, requiring films and overlay metrology systems with optical technologies and advanced modeling/algorithms that can accurately model and effectively measure structures on this substrate stack.

FinFET devices, largely used in high performance devices such as GPUs and CPUs, are in full production at the 45nm, 28nm, 16/14nm and 10nm logic design nodes, with 7nm finFET devices scheduled to release this year. FinFETs consist of an innovative 3D transistor architecture that allows IC manufacturers to produce devices with smaller feature sizes, higher speed and lower power consumption. Production of finFETs at 1Xnm design nodes involves the use of multi-patterning techniques, such as self-aligned quadruple patterning to achieve the desired device final dimensions, but dramatically increases the number of process steps required to produce the transistor. Process control for finFETs requires not only high sensitivity inspection and metrology systems to help address smaller critical defects and 3D device structures, but also high productivity to help cost-effectively monitor and control the increased number of process steps associated with multi-patterning.

With respect to the 3D transistor architecture of finFETs, the primary metrology challenge involves accurate measurement of the various parameters associated with device performance – such as, sidewall angle of the fin, thickness of complex film stacks, and pattern overlay error. With the use of multi-patterning techniques, overlay metrology systems must also be able to accurately and robustly provide feedback on both within-layer and layer-to-layer overlay error. Key metrology systems that support finFET production include:

  • SpectraShape 10K for measurement of device shape and critical dimensions
  • Archer 600 and ATL for overlay error measurements
  • SpectraFilm F1 for film thickness measurements

Because of the smaller dimensions and multiple process steps associated with finFET fabrication, defect inspectors require high resolution, optical filtering and algorithms for optimal extraction of defect signal from noisy pattern, and high throughput for full wafer coverage. With these attributes, the defect inspection and review systems combine to discover, identify and control very small critical defects across a range of process layers. To ensure that all critical defect types are being found, fabs implement a multi-faceted inspection approach, including:

  • In-fab reticle inspection to monitor and requalify reticles for critical defects that could impact every field printed
  • Versatile defect discovery methods using optical patterned wafer defect inspectors and e-beam review tools to find all systematic defect types and reveal wafer-level defect signatures that can help engineers identify the defect source
  • Inline and tool monitoring of critical defects to quickly identify excursions that affect yield

This comprehensive inspection strategy for finFETs allows engineers to characterize and monitor fab-wide processes, producing accurate information for determining corrective action.

By understanding each unique device architecture, process technology and specific layer of interest, IC manufacturer’s specific technical challenges can be addressed quickly and economically. KLA-Tencor’s extensive portfolio of inspection, metrology and data analytic systems are uniquely designed for fab-wide characterization and inline process control of advanced logic, planar bulk Si and SOI substrates, finFET devices, and 3D NAND and DRAM memory devices. We look forward to supporting our customers’ requirements and enabling their success.



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