The Importance Of Aging Simulation In IC Design

To ensure reliability, the need for corresponding aging models is increasing.


Electronics reliability has been an important quality criterion in the automotive sector and in industrial automation for years. Electronics in this sector have to achieve product lifetimes of 10+ years under partially harsh environmental conditions. But the reliability of electronics is also becoming more important in other fields. For example, end customers now keep consumer products longer, so a certain longevity is also expected in this area – albeit less strictly than in the automotive and industrial sectors. To achieve this reliability, it must be ensured that a system continues to fulfill the required performance even after a specific operating period. If electronic circuits and systems are operated for longer periods, they have to be replaced less often, which in turn supports the general trend towards greater sustainability.

Until now, the reliability of electronic systems has been investigated and verified as part of the qualification for the product or prototype. The AEC-Q100 standard, which defines test sequences for automotive applications, is of particular importance for integrated circuits (ICs). In testing, excessive loads in the form of stresses and temperatures, for example, are used in order to observe changes due to degradation within a reasonable period of time. Doubts are growing as to how testing and application conditions can be reconciled and what excessive loads are possible without altering the mechanisms that cause damage. The latter is of particular interest in terms of temperature because, for applications up to 175 °C, a further increase in temperature for test purposes often causes damage, e.g. to the materials used. This in turn often makes it unfeasible to transfer the test results to application conditions.

Reliability can be checked virtually more easily, more efficiently and with less material input. Such steps will never replace final testing and inspection of products, but they will efficiently identify problem areas and help to remedy them before the transition to production. The prerequisite for this is the availability of suitable processes and the models required for them.

Aging simulation is one such method and is now established in IC design. In particular, it supports developers of long-life circuits in achieving their reliability goals. The influence of transistor aging on circuit behavior through effects such as hot carrier injection (HCI) and bias temperature instability (BTI) is thereby simulated.

As a rule, the transistors in an IC are individually loaded with currents, voltages, and temperatures during operation. As a result, effects such as HCI and BTI also have individual repercussions. The extent of this load can be determined by simulating typical scenarios, so-called mission profiles. Aging models convert the individual load into individually changed transistor behavior and return this information to the simulator. This creates a virtually aged circuit that can be further investigated by simulation. Both the definition of mission profiles and the provision of aging models represent extremely complex tasks, and this paper focuses on the second aspect.

Fig. 1: Aging models between foundry, IC designer and EDA vendor.

Aging models occupy a place in the middle in the interaction among foundries, EDA vendors, and IC designers. IC designers are aware of the reliability requirements from the application as well as from the concepts and properties of their circuits. On this basis they can make claims with regard to the scopes of validity, influencing variables, and the accuracy of aging models. EDA tool vendors sometimes offer aging models that are built into their simulators, and these merely need to be configured for the target technology. In addition, interfaces are provided to connect custom aging models. For EDA tool vendors, model accuracy and complexity are practically irrelevant. Foundries, as owners of the technology, know its reliability particularly well. They typically provide aging models, and at least the initial aging models are available in a growing number of PDKs from different technology nodes, which underlines their growing importance.

A wide variety of factors make aging simulation an extremely complex topic, ranging from considerable effort for the characterization, parameterization, implementation and maintenance of the models, the multitude of transistors per technology, and the differing requirements of the IC designers. We receive the feedback that the designers’ requirements differ depending on the design project. For example, the various influencing variables (such as Vds, Vgs, T, geometry, …) and transistor parameters (such as IDLIN, IDSAT, VTH, GMA, IOFF) need to be recorded. Addressing all of these aspects in aging models requires a very high level of effort in characterization and complex model approaches, and thus a considerable deployment of resources. However, simplifications and standardizations will make aging modeling manageable.

The OMI simulator interface standardized by the CMC is already standardizing the connection of aging models to simulators. For the models themselves, physical approaches could add degradation mechanisms to the previously used compact models and create corresponding new standards. A more uniform approach in the area of empirical models is also promising. Regardless of which approach will prevail, there are still many steps to be taken in aging modeling. But research and development is already working intensively on solutions. At this point, users also have the opportunity to incorporate their requirements directly in order to obtain optimal support as quickly as possible in the design of their future circuits and in the systems of the future.

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