The Next Generation Of Wearables

Minimizing energy footprints requires co-design techniques for all the components, both soft and hard.


As the wearable market begins to take root, so has the focus on ultra-low power design—with some unique headaches that are unique to wearables.

To begin with, there is much attention being paid to this market because of the almost staggering predictions associated with it. While numbers vary greatly, IDC predicts as many as 126 million units will be shipping annually by 2019. The five-year compound annual growth rate is expected to be nearly 50% according to IDC. ABI predicts the market for wearables will reach $18 billion by 2019. And Juniper believes it will be worth $53 Billion by 2019. As far as the (aka Internet of Everything) goes, the wireless IoT sensor market alone will be worth $12 Billion by 2020, according to Radiant Insights.

There is no shortage of forecasts, broken out by any number of variables and components, but the point is that wearables and the IoT are likely to become one of the biggest markets for semiconductors in the next few years. With that in mind, there is a paradigm shift coming in powering these devices.

Challenges ahead
There are several challenges facing chip designers in this area. The balance between performance and power is well known, and there is a finite limit to what can be done with current chip technology. While single-electron gate devices are theoretically possible, other issues, such as leakage, become problematic and can thwart the purpose of such minuscule power designs.

“In today’s connected devices, we see a clear move away from using separate wireless combo chips toward integrating connectivity onto the main application processor as companies look to reduce power, footprint and bills-of-material,” said Takeshi Niwa, an analyst at Techno Systems Research.

That is an interesting perspective. If that trend is true, there will need to be a major realignment of design philosophies away from designing everything under the sun into single, multi-purpose chips to designing specific smart SoCs that focus on low-power functions.

“Low-power design is a prerequisite, and proper energy management must be addressed at the system level,” said Bernard Kasser, director of security R&D for advanced system technology at STMicroelectronics. “An IoT/E wireless sensor-node SoC, for example, must be capable of working with a range of operating modes that switch internal resources on and off as necessary to reduce energy consumption to sometimes even less than 1 microamp in idle modes. To get there, the chip must often be fitted with multiple power islands, various forms of body bias, retention modes, and other tricks.”

Because almost all nodes will rely on some sort of rechargeable energy, one problem that needs to be addressed is to design analog blocks to become ultra-power efficient. That is much more difficult than for digital blocks because they generally only consume significant power during clock cycles. Progress in that direction has been made in optimizing the functionality of the device. Various power conservation schemes, such as optimizing the duty cycle both in operation and frequency, are being implemented. In addition, there have to be new methodologies to tightly couple the low-power metric to designing low-power aware software stacks.

Another challenge is improving on the power sources themselves. Many applications, especially micro-sized devices such as Internet dust and motes will have to scavenge energy from the environment (RF, light, wind, piezo, and for some applications, thermoelectric and biomechanical). To make this happen with such low-energy sources, future designs will require tight coupling between the low-power demands in silicon and the low-power awareness in software designs.

A classic example of the conundrum of power vs. performance is the fitness band. Fitness bands have many functions and the processor is constantly analyzing data from the sensors. This is not the type of application where the device can be put to sleep for any appreciable time while in working mode. The sweet spot is to have a processor that has the speed to do decent MIPs/MHz at very low power consumption.

How to accomplish this is a balancing act, using the best component to fit the 80% part of the bell curve. For MCU design, there are a lot of options available. First of all, there are a number of options in register type and selection. In addition, parameters such as gate count, number of interrupts and the number of levels in the design all can be adjusted to attain the desired results. Program counter widths, divider count and widths also can be modified.

Low-power optimized MCU. Courtesy of Synopsys.

Low-power optimized MCU. Courtesy of Synopsys.

The designer can control bus types and widths, and specify external interfaces. And, finally, but not exclusively, code options can be set within the MCU. There are also other tricks that can be employed to reduce power. Clocks can be throttled up or down, processing can be clustered, and with some applications such as the fitness band, it really only has to run a couple ours at a time, and often less than that.

Some other methodologies that can be used to improve on power budgets include creating a sophisticated clock tree that allows gating of the clocks. This can help by allowing the software application to power down the peripheral when not in use. Furthermore, any applications must be aware of the power model and be able to put part, or all of the analog blocks, as well as the processor, to sleep during periods of inactivity.

One of the key design parameters for wearables and, in general, autonomous devices, is extensibility. Processors should have the ability to be able to link to any number of external components, such as an arithmetic co-processing block (arithmetic logic unit or ALU). This keeps the processor itself lean and mean, and it can be combined with any configuration of external components to support whatever type of application is desired.

The extensibility angle
Decentralization is a key design methodology for low-power designs. Until recently, it has been somewhat counterintuitive not to pack as much as one can into as small a footprint as one can. The mentality has been to put the feature pedal to the metal and make core components as functional as possible, on a single die. That philosophy has taken a 180-degree turn with the IoT.

Back to the fitness application—the number of measurable parameters can include heart rate, distance, pace, blood pressure, hydration and any number of other parameters. The processor should work only on the core functions, such as processing the data and sending it to a radio. The extensible vectors would include a Bluetooth Smart radio, a floating-point process for the number crunching, and a sensor interface that would filter and sort all the inputs before sending to the MCU.

Finally, intelligent programming that optimizes clock cycles to efficiently execute a step in the best possible sequences is the final piece of the puzzle.

The security angle
One of the challenges with low power is that it isn’t intrinsically compatible with security. By default, conflicts exist between security and low-power requirements. This will require vigilant analysis and design methodology to arrive at optimal system performance. Designing metal-level security into low power just adds another power demand to an already tight power budget. One can add the security as a software stack but most hardware security experts agree that security should be integrated into the fabric and not by the application or the OS.

Still, to the companies that solve these kinds of problems go the spoils. Frankwell Lin, president of Andes Technology, said the two key considerations for products are power consumption and security. “Most of these devices need some sort of processor, whether it’s an MCU, an embedded processor or a DSP. They also need wireless connectivity, which could be anything from Bluetooth to WiFi to ZigBee, and I/O for sensor input and output.”

Lin noted that while there has been a push on one hand to create building blocks for IoT devices, mixing power with security with reasonable performance points to more integration, probably on the same die instead of inside a package.

“Some types of these will be standalone, un-tethered devices that seldom connect to the network,” he said. “Other types, like the iWatch, will always be connected. Both types have a common requirement of long battery life—what we call “performance-efficiency—the need for security, since all are communicating machine-to-machine, and low-cost, since many applications such as smart lights are price-sensitive. The single greatest difference between the two types is communications capabilities. The ‘always connected’ types of devices will require support for a variety of communications, from NFC to WiFi and others. In many ways, ‘always connected’ makes wearable devices, from a semiconductor standpoint, a lot like low-power IoT devices. In that respect, it’s important to monitor the IoT device market requirement trends, to see how wearable devices can leverage it.”

Microcontroller OEMs say they are looking at adding dual-bank flash, hardware encryption blocks, and external devices specifically designed to sniff out contaminated code.

“We are used to scenarios where devices are available anytime and anywhere,” said Asaf Shen, vice president of products at Sansa Security. “However, that will not necessarily be the case for a lot of the IoT devices. Things like constant polling and keeping radios in ready mode will not work for many of the devices on the IoT within both power and security envelopes. “Devices will need to have very specific security, communication and frequency of event profiles cognizant of power related operation.”

For low-power scenarios the payload sizes, frequency of transmission and overhead must be optimized, regardless of the process node. Securing the transmission mode to fit into the power budget is also a must. Best power and security practices, as this evolves, will include particular (pseudo or completely random) challenge and response, power-optimized scenarios to verify the nodes before the actual control and data are sent to ensure that the target node is the authentic, intended recipient.

Going forward, the primary security design requirement for the IoT revolves around the Internet. Current designs primarily are focused on either standalone or closed-network systems. That makes security design much less complex. However, as IoT networks become “open,” security design will take on a new level of complexity. Open networks are an order or magnitude more vulnerable, and have another order of magnitude more of threats. That equates into a virtually bottomless bucket of security threats, to which more are added daily. Add in low power demands and it becomes even tougher to solve.

Progress in securing new and evolving low-power IoT devices is in the early stages. Security and low power, on the other hand, are fairly well along the experience curve. But integrating what we know well with what we haven’t seen much of yet, and do not have a deep well of experience with designing, creates a very challenging landscape. One promising theory is to set up nodes on a participatory premise, where nodes are able to interface with each other to interactively, and in real time, report all suspicious activity on the network. But this must be done in a very constrained code space, and the tight power budget raises its head again.

Current consensus is that the best thing to secure is the endpoint. And, best practice dictates that it be protected against current threats and be agile enough to be able to adapt to future threats – whatever that schematic looks like. Because there are some uncharted waters along the way, it still is a bit of a tall order – low power, security and the Internet. But, there is little doubt that, eventually, a workable model will evolve and a direction will ensue. The question is whether that’s before or after a major security breach.

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