Applied Materials names new CEO; Synopsys adds Dolby on ARC; Arteris wins China deal; Freescale rolls out comms processor with Cadence DFM; Mentor focuses on hybrid and electric vehicles.
By Ed Sperling
Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003, will become executive chairman of the board of directors. Dickerson was the CEO of Varian, which Applied Materials acquired in 2011.
Synopsys introduced a Dolby decoder for its ARC processor, which provides makers of TV and set-top box audio processors with support for all Dolby formats.
Arteris won a deal with China’s Allwinner Technology, which licensed its network-on-chip IP for tablet and mobile device SoCs.
Freescale Semiconductor taped out a 28nm 1.8GHz communications processor using Cadence’s DFM and signoff tools. The new SoC has hierarchical blocs and 12 Power Architecture 64-bit processors.
Mentor Graphics unveiled its agenda for the upcoming Integrated Electrical Solutions Forum for the automotive market. New this year is a track for electric and hybrid vehicle design.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Leaders of three R&D organizations, Imec, Leti and SRC, discuss the latest chip trends in AI, packaging and quantum computing.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
What could make this memory type stand out from the next-gen memory crowd.
Researchers digging into ways around the von Neumann bottleneck.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
This will go down as a good year for the semiconductor industry, where new markets and innovation were both necessary and rewarded.
The term creates hope for some, fear for others, and confusion for all.
Researchers digging into ways around the von Neumann bottleneck.
Optimizing processor architectures requires a broader understanding data flow, latency, power and performance.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
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