The Week In Review: Design

PCB design tool; 5G FEC IP; moving neural nets; online courses for Arm.


Altium released the latest version of its PCB design suite. Improvements include a new interface and an upgrade to 64-bit architecture combined with multi-threaded task optimizations. Other additions include a new BoM rule checker and length tuning and pin-swapping in the user-guided routing engine.

Creonic announced a new line of IP for 5G forward error correction. The product line covers the LDPC decoder as well as Polar encoder and decoder IP cores for the latest 3GPP specification, Release 15. The LDPC core comprises HARQ combining, rate matching, LDPC decoding, and CRC check. It supports base graph 1 and base graph 2 type LDPC codes with all code rates. The Polar decoder is designed for lowest latency requirements.

The Khronos Group debuted the Neural Network Exchange Format (NNEF) 1.0 Provisional Specification for universal exchange of trained neural networks between training frameworks and inference engines. The goal of the project is to reduce fragmentation of machine learning deployment by allowing transfer of trained networks from the training framework into a variety of engines. NNEF has been designed to be reliably exported and imported across tools and engines such as Caffe, TensorFlow, Theano, Chainer, Caffe2, PyTorch, and MXNet.

Arm Education Media launched two new online courses: Introduction to System-on-Chip Design, which focuses on building SoCs around ultra-low-power Arm Cortex-M0 DesignStart processors, and Advanced System-on-Chip Design, which goes through a typical advanced SoC design process using Arm Cortex-A based platform FPGAs. Each course contains 10-12 modules that cover lecture slides, quizzes, lab videos, project code and solutions.

Panasonic renewed its license agreement with Rambus for five years. The agreement covers products that include SoCs with DRAM memory controllers.

OneSpin returns with another holiday puzzle, this year challenging people to use formal tools to solve what may be the world’s hardest Sudoku grid. The deadline is Jan. 7th.

Early registration and an advance program are now open for next year’s DVCon, held Feb. 26-Mar. 1, 2018 in San Jose, CA. Features include tutorials on the Portable Stimulus Standard and UVM, a keynote on how new segments in the industry are changing verification, and a new slate of short workshops.

DAC’s Design and IP tracks are now welcoming presentation submissions. Topics include front-end design, back-end design, embedded systems and software, automotive, and security and IoT. The submission deadline is Jan. 23, 2018. The conference will be held June 24-28, 2018 in San Francisco, CA.

Leave a Reply

(Note: This name will be displayed publicly)