The Week In Review: Design

Microchip to buy Microsemi; Silvaco acquires NanGate; Arm’s graphics suite; AI processors; 8nm foundation IP.


Microchip inked an agreement to acquire Microsemi, provider of chips for defense and aerospace, for $68.78 per share in cash. The acquisition price represents a total equity value of about $8.35 billion and a total enterprise value of about $10.15 billion, according to Microchip. The deal is expected to close in the second quarter of 2018.

Silvaco acquired NanGate. Founded in 2004, NanGate provides a suite of tools focused on standard cell library optimization and characterization. The latest updates from the company have included a 2D compaction engine at the layout clean-up phase and the development of a new transistor ordering algorithm. Silvaco has been buying up companies at a rapid rate; last year it agreed to acquire Paripath, a company specializing in characterization software, as well as IP provider SoC Solutions.

Analog Devices acquired Symeo, a company that specializes in RADAR hardware and software for emerging autonomous automotive and industrial applications. Analog Devices anticipates incorporating Symeo’s signal processing algorithms on a RADAR platform with improvements in angular accuracy and resolution. Symeo was spun out from Siemens in 2005. Terms of the deal were not disclosed.

Arm launched a new suite of Mali video, display and graphics processors. The suite comprises the Mali-G52 and Mali-G31 GPUs, which targets DTV, mainstream, and entry-level mobile; the Mali-D51 Display Processor for higher screen complexity along with improved power savings and memory latency on mainstream devices; and the Mali-V52 Video Processor focused on 4K60/4K120 content on mainstream devices.

Kneron debuted its line of AI processors for edge devices. The KDP 300 is an ultra-low power version, the KDP 500 a standard version, and the KDP 700 a high-performance version, all consuming under 0.5W. The KDP 300, designed for facial recognition in smartphones, consumes less than 5mW. The energy efficiency of the entire product line is higher than 1.5 TOPS/W, according to Kneron. They support various types of CNN models such as Resnet-18, Resnet-34, Vgg16, GoogleNet, and Lenet, as well as mainstream deep learning frameworks, including Caffe, Keras, and TensorFlow.

Synopsys will develop foundation IP for Samsung’s 8nm Low Power Plus (8LPP) FinFET process technology. The IP will be designed to meet automotive Grade 1 temperature (‑40C to +150C junction) requirements and be ASIL D Ready. Qualified customers can license the IP at no cost.

CEVA uncorked Bluetooth 5 dual mode IP, which couples Bluetooth 5 low energy features such as LE 2Mbps, Long Range and LE Advertising Extension, together with the classic Bluetooth BR/EDR operation. The IP consists of a hardware baseband controller and software protocol stack. It targets smartphones, smart speakers, headsets, and IoT.

Synopsys added two encryption algorithms, ChaCha20 and Poly1305 (RFC7539), to its DesignWare Multipurpose Security Protocol Accelerator IP for IoT-focused SoCs. The IP supports efficient data sequencing as well as parallel processing of cryptographic operations such as authentication and encryption/decryption. Other features include Trusted Execution Environment (TEE) support, secure key access, and differential power analysis countermeasures.

An Early Adopter II release of Accellera’s Portable Test and Stimulus Standard has been made available by the Portable Stimulus Working Group for public review. The release includes additional work done by the working group since the release in June 2017 of the Early Adopter version, including user feedback from the earlier version. The review period runs through March 30, 2018.

Canaan-Creative employed Moortec’s In-Chip Monitoring Subsystem in the company’s new ASIC aimed at high-performance computing.

Arteris IP inked a deal with Dream Chip Technologies, which will license automotive reference development platforms that incorporate the Arteris IP FlexNoC interconnect with the FlexNoC resilience package as the communications backbone of the SoC designs.

ASICs Unlock Deep Learning Innovation: Mar. 14, 3:30 p.m. – 7:30 p.m., in Mountain View, CA. This seminar will explore an implementation platform for deep learning ASICs including HBM2 and 2.5D system-in-package design and implementation. The event is hosted by Samsung Electronics, Amkor, eSilicon, and Northwest Logic with a keynote by Ty Garibay, CTO of Arteris IP.

ISQED 2018: Mar. 13-14 in Santa Clara, CA. The conference highlights design techniques and methods, design processes, and EDA design methodologies and tools to improve the quality and manufacturability of ICs. Keynote speakers will address asymmetry in electronics, opportunities in AI, and recent materials and design innovations. Tutorials focus on power-aware test, power for IoT, and cyber-physical systems.

DATE 2018: Mar. 19-23 in Dresden, Germany. The conference focuses on hardware and software design, test and manufacturing of electronic circuits and systems. Features include in-depth tutorials, business panels, and keynotes on safety for autonomous vehicles and mapping circuits to DNA.

D&R IP-SoC Day: Apr. 5 in Santa Clara, CA. The one-day event will discuss trends in IP including AI and deep learning architectures, RISC-V, eFPGAs, and IP management and reuse.

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