The Week In Review: Design

Tools & IP
Cadence and National Instruments are teaming up with the aim of improving the semiconductor development and test process. The two companies are jointly working on common transistor models to ensure consistent simulation behavior between NI AWR Microwave Office circuit design software and the Cadence Spectre simulation platform. Cadence also launched the Virtuoso RF Solution for design, implementation, and analysis of RF modules and RFICs from within the Virtuoso custom IC design platform. It includes integration with the AXIEM 3D planar EM simulator.

SmartDV released verification IP for OpenCAPI, a high performance coherent bus standard for data center applications intended to allow FPGAs, GPUs, network and storage accelerators to perform functions that a server’s general purpose CPU is not optimized to execute.

Dolphin Integration launched a new Dual Port RAM compiler in TSMC 40nm. The compiler is capable of generating instances ranging from 64 bits to 288 kbits and features a ultra-low leakage stand-by “NAP” mode, allowing a leakage reduction of up to 35% compared to standard stand-by modes with a single clock cycle wake-up time.

Chipus uncorked its third generation of battery charger IP. Now being fabricated in SilTerra 0.18um BCD (D18V), it is designed to consume down to 40 nA in OFF mode (or battery supply mode) and features a programmable output voltage to deal with different battery types as well as a bi-directional power switch.

Lattice debuted sensAI, a technology stack combining modular hardware kits, neural network IP cores, software tools, reference designs and custom design services intended to support integration of machine learning inferencing into broad market IoT applications. It is optimized for ultra-low power consumption (under 1 mW–1 W), small package size (5.5 mm2 –100 mm2), and interface flexibility.

Certifications
Synopsys’ Design Platform has been certified for Samsung Foundry’s 8nm LPP (Low Power Plus) process. The platform provides full-flow support for multi-patterning and full color-aware variation for the 8LPP process. The 64-bit Arm Cortex-A53 processor, based upon the Armv8-A architecture, was used for QoR optimization and flow certification.

Mentor’s Tessent design-for-test products have been certified for Samsung Foundry’s 8nm LPP process. The Samsung Foundry Solutions reference flow includes TestKompress scan compression logic and Tessent ScanPro on-chip clock controllers automatically inserted early in the register transfer level (RTL) design stage.

Cadence’s full-flow digital and signoff tools have been certified for Samsung Foundry’s 8nm LPP process. The Cadence RTL-to-GDSII design flow that has been certified for the 8LPP process technology is based on the Design Methodology (DM) of Samsung Foundry using an OpenRISC OR1200 design. The tools are available via a quick-start kit.

Mentor’s Nucleus SafetyCert real-time operating system (RTOS) achieved the safety certifications for IEC 61508 SIL 3 industrial applications and IEC 62304 Class C medical devices from TÜV SÜD.

Numbers
Synopsys reported second quarter financial results with revenue of $776.8 million, up 14.2% from the second quarter of 2017. On a GAAP basis, earnings for Q2 2018 were $0.67 per share, up 97% from $0.34 per share for the same quarter last year. Non-GAAP income for the quarter was $1.08 per share, up 22.7% from $0.88 per share in Q2 2017. The company raised revenue and non-GAAP earnings per share guidance for the year, now expecting $3.07 billion – $3.10 billion in revenue.

If you attended DAC in 2017 and caught Joe Costello’s keynote, his company, Enlighted, has been acquired by Siemens’ Building Technologies Division. Enlighted provides an IoT sensor platform to aid in space planning and asset tracking for commercial real estate.