The Week In Review: Design

SoftBank to sell 25% stake in ARM; task graphs for virtual prototyping; automated interconnect timing closure; LPDDR4 update.


SoftBank plans to sell a 25% stake in ARM to Vision Fund, a $100 billion technology fund created last year by SoftBank and Saudi Arabia’s Public Investment Fund. SoftBank and Saudi Arabia are investing $25 billion and $45 billion in the fund, respectively. Another potential major player is Mubadala Development Co., the government-owned Abu Dhabi investment firm which owns GlobalFoundries and, at 10.3%, is the single largest shareholder in AMD. Mubadala is reportedly considering investing up to $15 billion in the fund. The ARM stake is being valued by SoftBank at $8 billion.


Synopsys introduced Task Graph Generator technology for virtual prototyping, which automatically extracts key performance characteristics from software applications, allowing a software workload model generated by the tool to be mapped to the processing resources in the candidate SoC for architecture exploration and performance and power optimization. In particular, it targets next generation multicore SoCs.

Mentor Graphics uncorked its new Xpedition vibration and acceleration simulation product for PCB systems reliability and failure prediction. Capabilities include detection of components on the threshold of failure that would be missed during physical testing and analysis of pin-level Von-Mises stress and deformation to determine failure probability and safety factors.

ARM debuted its new debug and trace solution, CoreSight SoC-600, to offer debug and trace over functional interfaces such as USB, PCIe or wireless, reducing the need for hardware debug probes while increasing data throughput.


Arteris launched a new product to automate interconnect timing closure for both cache coherent and non-coherent subsystems. The solution, PIANO 2.0, calculates the length of individual interconnect links and traces, and uses information about the technology process and performance targets to automatically add interconnect pipelines to close timing. It helps validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence tool chains.

Synopsys revealed ASIL D Ready certified dual-core lockstep processors with integrated safety monitors. The processors can operate in either lockstep mode for ASIL D applications or independent dual-core mode to optimize performance for ASIL B applications, and include a programmable watchdog timer to help detect system failures and runtime faults.


JEDEC released a new revision of the LPDDR4 standard focused on higher performance, which includes the addition of a single-channel die option for smaller applications, new MCP, PoP and IoT packages, and additional definition and timing improvements for the highest 4266 Mbps speed grade. An optional extension, the new LPDDR4X standard, was also announced. LPDDR4X is intended to offer product designers options for further power reduction as well as on die termination (ODT) flexibility.


Western Digital inked a patent license agreement covering the use of Rambus’ memory technologies, including high-speed interfaces, memory architectures, resistive memory and security technologies, in Western Digital products through 2021.


The ESD Alliance will present a special panel discussion focused on the California Energy Commission’s new energy efficiency rules for PCs and monitors and what they mean for the semiconductor design ecosystem. The event will be held Thursday, March 23, 2017, from 6pm-9pm at the San Jose City Hall Rotunda.

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