The Week In Review: Design

IP
Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching.

Cadence launched a new DSP architecture, Tensilica HiFi 3z. The new architecture offers 1.3X better voice and audio processing performance than its predecessor, the company said. Other enhancements include dual load/store, advanced FLIX bundling, double the MACs for 16×16 (octal MAC), an enhanced ISA for accelerating FFTs, FIRs and IIRs, and new instruction extensions to improve codec performance for mobile. The DSP targets smartphones, AR/3D goggles, TVs, and set-top boxes.

Inside Secure released new 400G MAC layer security IP cores for Ethernet encryption. The MACsec IP supports all packet transformations and packet sizes and natively includes multi-channel support with fully-flexible bandwidth allocation.

Embedded
Mentor updated its embedded product portfolio, adding coverage for the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. The release also includes an updated version of Mentor’s embedded development environment and trace support for ARM Cortex-A53 application processes running Mentor Embedded Linux or Nucleus RTOS, and Cortex-R5 safety processor running Nucleus RTOS or bare metal.

Standards
The USB 3.2 update is on the horizon. The incremental update defines multi-lane operation for new USB 3.2 hosts and devices, allowing for up to two lanes of 5 Gbps or two lanes of 10 Gbps operation. Existing USB Type-C cables designed to support multi-lane operation (certified for SuperSpeed USB 10 Gbps) will see effectively doubled performance. The specification is in draft release, with a formal release by September’s USB Developer Days.

Deals
MediaTek adopted Synopsys’ HAPS-80 prototyping system for its next generation of SoCs. MediaTek cited the ability to execute a large number of software tests and perform real-world interface testing.

Events
DVCon is now accepting extended abstracts and panel proposals for next year’s conference. Extended abstracts should be highly technical and reflect real-life experiences and emerging trends in various domains. The deadline for abstract submissions is August 8. The deadline for panel proposals is September 29. DVCon 2018 will be held February 26-March 1 at the DoubleTree Hotel in San Jose, California.

Numbers
Cadence reported second quarter financial results with revenue of $479 million, up 5.7% from the second quarter of 2016. On a GAAP basis, income per share stood at $0.25, up 47% from $0.17 per share in Q2 2016. Non-GAAP income for the quarter was $0.34 per share, up 17% from $0.29 last year. Digital and signoff revenue was up 14%, while IP was up 15%. For the third quarter, the company expects revenue in the range of $475 million to $485 million.

Rambus released second quarter financial results with revenue of $94.7 million, up 24% from the same quarter last year. On a GAAP basis, income per share for Q2 2017 was $0.02, down 33% from $0.03 in Q2 2016. Non-GAAP income per share was $0.14, down 6.7% from $0.15 for the same quarter last year. Revenue growth was particularly strong for memory and interfaces (24%) and security (42%). For the third quarter, the company expects revenues between $96 million and $102 million.