The Week In Review: Design/IoT

Mentor adds tool for IC, package, PCB co-design; Synopsys debuts tool for ASIP design; Rambus inks deal with IBM; NXP to set up smart biz district in Shanghai; Intel, Micron roll out 3D NAND.



Mentor Graphics uncorked its new IC, package, and PCB co-design and optimization product. It includes a formal flow for ball grid array ball-map planning and optimization based on an “intelligent pin” concept and a multi-mode connectivity management system for cross-domain pin-mapping and system level cross-domain logical verification.

Synopsys released a new tool for designing ASIPs and programmable accelerators. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++-compiler based software development kit that automatically adapts to architectural changes, and automatic generation of power and area-optimized synthesizable RTL.


Rambus inked patent and technology license agreements with IBM, involving Rambus’ memory controller, serial link interface technologies and memory interface design IP.

NXP Semiconductors signed a memorandum of understanding with a commercial real estate developer in China, B.M. Holding Group and an ISP, Digital China Holdings, to create a 1 square kilometer smart business district in the center of Shanghai that is based on wireless networking technology. Construction is expected to be completed in 2017. It will support near-field communications, smart furniture, community illumination, resource control and safety monitoring. NXP also moved to centralize its operations in China to improve its ability to make decisions involving strategic investments and financial management.

Micron and Intel rolled out new 3D NAND that uses floating gate cells. The companies claim it is the highest-density flash device ever developed, providing up to 10 terabytes of storage in the standard 2.5-inch solid state drive format.

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