Synopsys beefs up verification tools; Cadence enhances PCBs; Mentor proposes graph-based test standard; plus, deals, partnerships and acquisitions.
Tools
Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio.
Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as much as 67%.
Standards
Mentor Graphics proposed that a new Accellera committee be formed to investigate ways to standardize graph-based test. Mentor said it would make a technical donation of its own spec format to get the effort started.
Accellera awarded Andy Goodrich, a member of the SystemC language working group, a technical excellence award. Goodrich, who is a senior member of the consulting staff at Cadence, was chief developer of the SystemC proof-of-concept simulator for ESL.
Deals
Arteris won a deal with Spreadtrum, which will use Arteris’ NoC IP for smartphone SoCs.
Atrenta won a deal with Sonics, which will use Atrenta’s constraints tools to enhance its IP signoff flow.
Sonics, meanwhile, inked a deal with Duolog Technologies to support adoption of IP-XACT design flows for their common customers.
M&A
Synopsys bought Brandenburg, which makes software for designing automotive light reflectors, as well as general lighting.
Intel struck a deal to buy Basis, which makes smart watch technology, according to TechCrunch. The move will put Intel into the wearable technology market, particularly for sensors. How Intel will use that technology remains to be seen.
Silicon Labs bought Touchstone Semiconductor‘s low-power analog IC products for its push into the Internet of Things. The sale price was $1.5 million, and includes everything from op-amps to LP A-to-D converters and power management ICs.
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