Tri-Gate’s Fallout

By David Lammers
Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied.

Now that Intel has come out of the closet with its tri-gate technology, “the foundry customers are all going to ask, ‘When am I going to get a FinFET? What does it look like?’” said one source, who asked not to be identified.

What they may find is a transistor that is rather difficult to build, at least for the companies that lack the resources to make the jump from planar to vertical structures. “Intel’s competitors will all be taking that thing (the tri-gate device) apart. They will learn from it. They will catch up, but it is not automatic and takes time. Intel has shown its technology leadership, but of course they have to invest an enormous amount of money to stay ahead and the competitors have to spend a much smaller amount to copy,” the source said.

Opinions differ on how quickly finFETs will enter the SoC space. At the Intel tri-gate rollout, Intel architecture general manager Dadi Perlmutter said Intel’s goal is to achieve “parity,” rolling out MPUs and SoC products on the latest technology at the same time. The lag is declining node by node, he said.

Planar vs. FinFET

Analyst Nathan Brookwood, sees Intel introducing tri-gate-based, 22nm, Atom-based SoCs for smartphones and tablets in the fourth quarter of 2012. Those “Silvermont” SoCs would be supplanted in 2014 by the 14nm-based “Airmont” SoCs. If that scenario proves accurate, Intel will be on the market with Atom-based and MPU products at the same time in 2014.

If Intel meets its target, and if TSMC rolls its finFET technology in 2015 at the 14nm node, at least two companies would be on vertical transistors for SoCs. There is speculation that TSMC might pursue a planar transistor for low-cost applications at the 14nm generation, using finFETs for the high-performance graphics MPUs, FPGAs, and others. And some believe that Intel will be more active in the foundry space, partly as a way to monetize the estimated $2 billion it took to develop the 22nm tri-gate technology.

Dean Freeman, a manufacturing technology analyst at Gartner Inc., said Intel’s tri-gate technology is impressive. “However, the SOI group won’t give up any ground.” The SOI consortium is working closely with ARM to demonstrate lower power consumption, at 1 to 2 GHz performance, for smart phones. But Freeman said most of those smartphone chips are produced on bulk wafers today, and they will be reluctant to spend much on the additional wafer cost represented by UTB-SOI wafers. Even AMD has switched to bulk (non-SOI) technology for its low-cost Fusion products, he noted.

On the other hand, Freeman said the vertical devices require a big change in the design tools, and a complete redesign of a company’s proprietary intellectual property. “Not all devices need 3D. Tri-gate will be used for Intel’s X86 products, and IBM will go 3D for its high-performance devices. Some high-performance ASSPs might need 3D as well. I am not certain about the ARM devices,” he said.

Gary Patton, an IBM vice president who manages the Fishkill Alliance including Samsung, Toshiba, STMicro, and GlobalFoundries, said the alliance is developing several different transistors for the 14nm node. IBM will continue to develop an SOI technology with finFET transistors, adding its on-chip SOI-based embedded DRAM technology. Other members of the alliance need a bulk FinFET, and others, including STMicroelectronics, are pursuing a planar UTB-SOI approach (which IBM refers to as Extremely Thin (ET)-SOI) using back-gate biasing underneath the planar channel to boost performance or reduce power consumption.

“ET-SOI with a back-bias operation is pretty comparable with finFETs for certain applications. FinFETs are pretty complex, and ST Micro is pretty confident in ET-SOI,” Patton said during a brief interview at the Advanced Semiconductor Manufacturing Conference, held in Saratoga Springs, N.Y., this month. Patton said members of the Fishkill Alliance and IBM Albany will give three papers at the upcoming VLSI Symposium, planned for early June, on SOI finFETs, bulk finFETs and ET-SOI.

“FinFETs have some performance advantages, but Intel and others will have to show that they can control the tolerances, including at the source and drain regions. On the other hand, ET-SOI appears to have some resistance problems, so we’ll have to see how it plays out,” Patton said.

Freeman said the Fishkill Alliance has been a huge success, but warned that the shift to a tri-gate transistor “does give Intel a crack at the mobile device market, as the power consumption is very good.”

The Gartner analyst added, “What IBM needs to look out for is an Intel alliance forming. You already have Toshiba and Samsung working with Intel on some transistor technology, so there could be some cracks forming. There is the possibility of two camps, but Intel is so protective of its IP it will be interesting to see how this plays out.”

Chenming Hu, who led a UC Berkeley team that did much of the early work on both finFETs and UTB-SOI a dozen years ago, said he believes for finFETs and UTB-SOI technology will be deployed. Manufacturing finFETs, with the need for a very thin fin at close tolerances, is challenging for all but the largest companies such as Intel and TSMC.

“If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

UC Berkeley's Hu

“I remain steadfast in my belief that both FinFETs and UTB-SOI will be going to manufacturing,” Hu said. “I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI. FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries. In FinFETs, the gate widths are discrete, rather than continuous. And the thickness of the fin needs to be scaled, along with the gate length.”

Scott Thompson, a professor at the University of Florida, said the manufacturing challenges of finFETs may provide Intel with a five-year lead, or longer.

“Developing a complex technology like tri-gate requires significant investment in silicon resources and manpower—development teams of perhaps more than 1,000 people. The complexities for development mean that hundreds of thousands of wafers have to be run to solve the issues. The tri-gate development is at least an order of magnitude more complex than strained silicon at 90nm, or HKMG at 45nm. That is why it took Intel eight years to implement, and why I don’t think anyone else will have in market for more than five years,” said Thompson, who spent two decades in technology development at Intel’s technology and manufacturing group at Hillsboro, Ore.

Manufacturing perfect fins over billions or trillions transistors is quite a challenge, Thompson said, adding that “it can be done in a fab that runs a single process, with equipment and settings that are kept constant. The manufacturing flow has unique advantages for high-end processors but does have problems supporting several key features needed for SOCs: multiple threshold voltages, and thin and thick oxides in support of analog.”