TSMC Tech Tour De Force

TSMC held the first of its three North American Tech Symposiums on April 7 in San Jose, with the other two coming up in Boston on April 14 and in Austin on April 16. As was mentioned previously here, the record fast ramp-time of the 20nm node was highlighted among other technological achievements. TSMC also released its March revenue report on April 10, and it shows a dramatic 49.8% increase in revenue for the first 3 months of 2015 vs. the first 3 months of 2014.

Table 1. TSMC March 2015 Revenue

TSMC’s North American President Rick Cassidy opened the event by mentioning that for 2014 North America accounted for the equivalent of 5.1 Million 12” wafers, 5,066 products and 74% of TSMC’s Q4 revenue. Cassidy also said 10nm is ahead of schedule. The 20nm node seems to be leading a charge of new technologies driving D0 (defect densities) down much faster with 16nm D0 now reported at 0.18. (It also should be noted that the units for this variable are 1/area and that some of the slides presented didn’t label the units on the axis, but one slide that did showed it as 1/inches^2). Current D0 was claimed to be at 0.05 for 28nm and higher nodes with some processes touching D0 = 0.03.

J.K. Wang, TSMC’s vice president of operations for 300mm fabs, said that N20 (20nm) had a D0 < 0.2 at the start of high-volume manufacturing (HVM) and less than 0.1 in 3 quarters after production. N20 only took 3 months to reach 60K wafers/month in volume. N16 (16nm finFET) is expected to better N20 and have a D0 < 0.15 by HVM. Capital Expenditures for 2015 are projected to be in the range of $11.5B to $12B, which will keep capacity ramping at a brisk pace. TSMC President and Co-CEO Mark Liu said that 16nm FinFET Plus will have more than 50 tapeouts by the end of 2015 and have 50% less total power over TSMC’s 20nm SoC process at the same speed. TSMC’s 10nm has demonstrated 256Mb SRAM yields with 2.1x the density of 16nm and 10nm will enter risk production in Q4 of 2015. A new 16nm process targeting “wearables” — called 16FFC (“C” for compact) — will have a nominal voltage of 0.55V, reduce power > 50%, with product tapeouts targeted for the second half of 2016. Investment in R&D is projected to increase from $1.9B in 2014 to $2.2B in 2015.

TSMC has a family of processes targeted for the Internet of Things (IoT) under the ultra-low power (ULP) label. B.J. Woo, vice president of business development, said TSMC expects IoT to have a compound annual growth rate (CAGR) of 30% from 2012 through 2017. She also mentioned that the two largest limiting factors for smartphones were batteries (i.e. amount of stored energy) and heat (i.e. no one wants to hold a toaster in their hand next to their head). TSMC also lists processes under two other categories labeled high-performance (HP) and mainstream.

At the moment, 28LP, 28HPL and 28HPC all fall under the “mainstream” category with 28HPC+ and 16FFC scheduled there for the future. 16FFC will also be considered part of the ULP line though too. 28HPC+ is expected to have a 15% performance gain (at the same leakage) over 28HPC. Woo also claimed that 28ULP will be better than the competition’s FDSOI processes, with a chart showing a comparison at a nominal voltage of 0.9V.

TSMC also has its first 28nm automotive qualified process that is compliant with AEC-Q100 grade-1 specification that Woo said was two orders of magnitude tighter reliability than for consumer electronics. The increased reliability requirements shouldn’t be too surprising, though, given the extremes that an automotive environment entails as well as the expected reliability for an automobile. Many consumer electronic products may be obsolete in three to four years anyway, so if it fails replacing it may not be that big of a deal. The expectations for an automobile are typically much higher. Woo mentioned that 20nm ramped five times faster than 28nm. Given that the 16nm finFET process shares the same BEOL with 20nm and will be ramping in the same fab as 20nm, the projections are for a fast ramp of 16nm as well.