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Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Researchers demonstrate “a low-voltage organic ternary logic circuit, in which the organic HTR was vertically integrated with the organic nonvolatile flash memory.”

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Research paper from KAIST and Gachon University.

Abstract

“Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~VDD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (<5 V). The organic flash memory exhibits long retention characteristics (current change less than 10% after 104 s), leading to the long-term stability of the 3D T-inverter. We believe the 3D T-inverter employing flash memory developed in this study can provide a useful insight to achieve high-performance MVL circuits.”

Find the open access technical paper here.  Published April 2022.

Choi, J., Lee, C., Lee, C. et al. Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors. Nat Commun 13, 2305 (2022). https://doi.org/10.1038/s41467-022-29756-w

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